Taiwan Semiconductor Manufacturing Comp. Ltd.

Globalwafers Co., Ltd.

Chun-Sheng Wu

Yi-Fang Li

Chun-Li Lin

Ding-I Liu

Geng-Shuoh Chang

Po-Hsiung Leu

William L Luter

Carissima Marie Hudson

Sumeet S Bhagavat

Yung-Tsun Liu

Feng-Chien Tsai

Yu-Chiao Wu

Chieh Hu

Hong-Huei Huang

Hsien-Ta Tseng

Liang-Chin Chen

Wei-Chen Chou

Zheng Lu

Kai-Shiung Hsu

Benjamin Michael Meyer

Jia-Wei Xu

Yl-Fang Li

Chen-Yi Lin

Yin-Bin Tseng

Jing-Yang Li

Ingot puller apparatus that include a silicon feed tube for adding solid silicon to a crucible assembly are disclosed. The silicon feed tubes include a conduit portion having an inner diameter and a kick plate disposed below the conduit portion. The kick plate extends across at least 60% of the inner diameter of the conduit portion.

Ingot puller apparatus having silicon feed tubes with kick plates

Contamination from outgassing during a deposition process is addressed by a series of equipment enhancements, including throttle valves, a dual air curtain, and a residual gas analysis (RGA) monitor. The dual air curtain can be configured to flow a first gas during wafer processing and a second gas during wafer unloading, to re-direct and capture outgassed species. The dual air curtain and the throttle valves can be programmed in an automated feedback control system that utilizes data from the RGA monitor.

Split valve air curtain

A susceptor assembly for supporting a crucible during a crystal growth process includes a susceptor base, a tubular sidewall connected to the susceptor base, and a removable sacrifice ring interposed between the susceptor base and the sidewall. Each of the susceptor base and the sidewall is formed of a carbon-containing material. The susceptor base has an annular wall and a shoulder extending radially outward from an outer surface of the annular wall. The sidewall has a first end that receives the annular wall to connect the sidewall to the susceptor base. The sacrifice ring has a first surface that faces the outer surface of the annular wall, a second surface that faces an interior surface of the sidewall, and a ledge extending outward from the second surface that engages the first end of the sidewall.

Single crystal growth susceptor assembly with sacrifice ring

A method of growing a single crystal ingot includes growing a single crystal silicon ingot from a silicon melt in a crucible within an inner chamber, adding a volatile dopant into a feed tube, positioning the feed tube within an inner chamber at a first height relative to a surface of the melt, adjusting the feed tube within the inner chamber to a second height at a speed rate, and heating the volatile dopant to form a gaseous dopant as the feed tube is moved from the first height to the second height at the speed rate. Each of the second height and the speed rate are selected to control a vaporization rate of the volatile dopant. The method also includes introducing dopant species into the melt while growing the ingot by contacting the surface of the melt with the gaseous dopant.

Systems and methods for controlling a gas dopant vaporization rate during a crystal growth process

A method includes a patterned hard mask layer formed over a substrate. The substrate is etched using the patterned hard mask layer to form a trench therein but leaving at least one elongated portion of the substrate inside the trench. A first isolation layer is formed over the patterned hard mask layer. The first isolation layer fills the trench and covers the at least one elongated portion of the substrate. A portion of the first isolation layer is removed to expose the at least one elongated portion of the substrate. The at least one elongated portion of the substrate is thereafter removed to form a first opening. A second isolation layer is formed over the first opening, the patterned hard mask layer, and the first isolation layer, the second isolation layer sealing the first opening to form an air gap.

Semiconductor device having a shallow trench isolation structure and methods of forming the same

A method for forming a semiconductor device is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming a contact plug in the dielectric layer. The method also includes partially removing the contact plug to form a recess over the contact plug. The method further includes forming a capacitor element in the recess.

Formation method of semiconductor device with embedded capacitor

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The semiconductor device structure includes spacers over opposite sidewalls of the gate stack. The spacers and the gate stack surround a recess over the gate stack. The semiconductor device structure includes a first insulating layer over the gate stack and an inner wall of the recess. The semiconductor device structure includes a second insulating layer over the first insulating layer. Materials of the first insulating layer and the second insulating layer are different, and a first thickness of the first insulating layer is less than a second thickness of the second insulating layer.

Structure and method of semiconductor device structure with gate

A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device also includes a contact plug in the dielectric layer, and a recess extending from a surface of the dielectric layer towards the contact plug. The semiconductor device further includes a capacitor element in the recess and electrically connected to the contact plug.

Structure and formation method of semiconductor device with embedded capacitor

The present disclosure provides a semiconductor structure, including a substrate, a metal gate, a dielectric layer, and an etch stop layer. The metal gate is positioned on the substrate and possesses a first surface. The dielectric layer surrounds the metal gate and possesses a second surface. The etch stop layer is in contact with both the first surface and the second surface. The first surface is higher than the second surface. The present disclosure also provides a method for manufacturing a semiconductor structure, including forming a dummy gate on a substrate; forming a second etch stop layer over the dummy gate; forming a dielectric layer over the dummy gate; replacing the dummy gate with a metal gate; etching back the dielectric layer to form a second surface of the dielectric layer lower than a first surface of the metal gate; and forming a first etch stop layer over the metal gate and the dielectric layer.

Metal gate structure

A semiconductor structure includes a semiconductor substrate, a dielectric layer formed over the semiconductor substrate, a first anti-etch layer, a second anti-etch layer and a conductive material. The dielectric layer has an opening. The first anti-etch layer is formed on the sidewall of the opening and made of a material having resistance to peroxide. The second anti-etch layer is formed over the first anti-etch layer and made of a material having resistance to acid. The conductive material is formed within the opening and in contact with the second anti-etch layer.

Semiconductor structure with anti-etch structure in via and method for manufacturing the same

The description relates to a method of patterning a semiconductor device to create a through substrate via. The method produces a through substrate via having no photoresist material therein. An intermediate layer deposited over an interlayer dielectric prevents etching solutions from etching interlayer dielectric sidewalls to prevent peeling. The description relates to a semiconductor apparatus including a semiconductor substrate having a through substrate via therein. The semiconductor apparatus further includes an interlayer dielectric over the semiconductor substrate and an intermediate layer over semiconductor substrate and over sidewalls of the interlayer dielectric.

Growing community of inventors

Hsinchu, Taiwan

Chun-Sheng Wu