Skhynix Inc.

Hynix Semiconductor Inc.

Industry-university Cooperation Foundation Hanyang University

Chun Seok Jeong

Jae Jin Lee

Chang Sik Yoo

Jang Woo Lee

Seok Joon Kang

Mun Gyu Son

Chang Hyun Kim

Seung Hun Lee

Jung Hwan Lee

Tae Sik Yun

Se Jun Kim

Kee Teok Park

Doo Bock Lee

Hyun Sung Lee

Hong Jung Kim

Yong Hoon Kim

Wan Jun Roh

A processing-in-memory (PIM) device includes a multiplication-and-accumulation (MAC) circuit, a memory circuit, and an address pipeline circuit. The MAC circuit is configured to perform a MAC arithmetic operation or an element-wise multiplication (EWM) calculation for first input data and second input data to generate result data. The memory circuit is configured to output the first input data and the second input data to the MAC circuit in response to a read control signal and is configured to store the result data in response to a write control signal. The address pipeline circuit is configured to receive the read control signal to store an address signal used as a target address signal for designating a region of the memory circuit into which the result data are stored. In addition, the address pipeline circuit is configured to receive the write control signal to output the target address signal to the memory circuit.

Processing-in-memory devices for element-wise multiplication

In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.

Image synchronization device and image information generation apparatus including the same

In accordance with an embodiment of the present disclosure, a semiconductor system includes a first semiconductor device coupled to a first transmission line, and configured to transmit a first packet to a second transmission line on the basis of first destination information of the first packet received through the first transmission line; a second semiconductor device coupled to the first semiconductor device through the second transmission line, and configured to transmit a second packet to a third transmission line on the basis of second destination information of the second packet received through the second transmission line; and a third semiconductor device coupled to the second semiconductor device through the third transmission line, coupled to the first semiconductor device through the first transmission line, and configured to transmit a third packet to the first transmission line on the basis of third destination information of the third packet received through the third transmission line.

Semiconductor device and semiconductor system including the same

A processing-in-memory (PIM) device includes a multiplier circuit, a memory circuit, and an address pipeline circuit. The multiplier circuit is configured to perform an element-wise multiplication (EWM) calculation of first input data and second input data to generate result data. The memory circuit is configured to output the first input data and the second input data to the multiplier circuit in response to a read control signal and is configured to store the result data in response to a write control signal. The address pipeline circuit is configured to receive the read control signal to store an address signal used as a target address signal for designating a region of the memory circuit into which the result data are stored. In addition, the address pipeline circuit is configured to receive the write control signal to output the target address signal to the memory circuit.

A memory system and a method for operating the same, wherein the memory system includes a first memory and a second memory each configured to store data. The memory system further includes a test and repair circuit operationally connected to the first memory and to the second memory. The test and repair circuit is configured to receive a test initiation signal and perform, in response to receiving the test initiation signal, a test operation on at least one of the first memory and the second memory. The test and repair circuit is also configured to perform, based on a result of the test operation, a repair operation on the at least one of the first memory and the second memory.

Memory system for improving memory reliability and memory management method for the same

A semiconductor apparatus includes a direct access section, an interface section, and a through-via region. The direct access section receives first and second groups of input signals through a direct access pad, and generates first and second groups of control signals based on the first and second groups of input signals. The interface section comprises a plurality of channel circuits suitable for receiving a part or all of the first and second groups of control signals in response to a plurality of channel selection signals. The through-via region electrically couples the plurality of channel circuits and a plurality of stack dies to form a plurality of channels, respectively.

Semiconductor apparatus and system including plurality of channels

A latch circuit may be provided. The latch circuit may include a plurality of latches configured to store and output data through input/output signal lines according to input/output control signals. Latches coupled with input/output signal lines of same orders among the plurality of latches may be disposed by being distributed by orders of the input/output control signals. A plurality of pipe latches may be configured by latches which are inputted with input/output control signals of same orders, among the latches disposed by being distributed.

Latch circuit and semiconductor apparatus including the same

An embodiment may include a first replica driver group configured for replicating an output driver of a physical area. A second replica driver group configured for replicating an output driver of a test electrode area for direct access of a memory, and an impedance calibration unit configured to independently perform an impedance matching operation of the first replica driver group and the second replica driver group.

Impedance calibration circuit, and semiconductor memory and memory system using the same

A semiconductor apparatus includes a command decoding unit configured to decode an internal command, an internal clock and an internal clock enable signal, and generate an internal control signal; a clock enable signal control unit configured to receive a pre-clock enable signal and output one of the pre-clock enable signal and an enabled internal clock enable signal as the internal clock enable signal in response to a first test signal; an enable signal selection unit configured to output one of the pre-clock enable signal and a second to test signal as a counting enable signal in response to the first test signal; and a counting unit configured to perform a counting operation during an enable period of the counting enable signal, and output a counting code.

Semiconductor apparatus

A semiconductor apparatus includes a direct access section, an interface section, and a through-silicon via region. The direct access section receives a normal clock, a first clock, and a control signal through a direct access pad. The interface section comprises a plurality of channel circuits suitable for aligning the control signal to the first clock, and outputting an aligned control signal. The through-silicon via region transfers the normal clock and the aligned control signal from the interface section to a plurality of channels corresponding to the respective channel circuits.

A semiconductor apparatus includes a TSV formed to be electrically connected with another chip and a TSV test unit configured to check a capacitance component of the TSV to generate a TSV abnormality signal.

Semiconductor apparatus and stacked semiconductor apparatus for checking formation and connection of through silicon via

A semiconductor apparatus includes a through via and a comparison unit. The through via is electrically connected with another chip. The comparison unit includes a reference capacitor, and compares a capacitance value of the through via and a capacitance value of the reference capacitor in response to a test start signal and a reset signal and generates a comparison result.

Semiconductor apparatus and testing method thereof

A pipe latch control circuit and a semiconductor integrated circuit using the same are provided. The pipe latch control circuit includes a read command control unit that receives a first signal and generates a read signal in response to a control signal. In the pipe latch control circuit, the read command control unit selects, in response to the control signal, the first signal or selects a second signal obtained by delaying the first signal according to an internal clock, and generates the selected first or second signal as the read signal.

Pipe latch control circuit and semiconductor integrated circuit using the same

A data equalizing circuit includes an equalizer configured to output data according to a control code; and a detection unit configured to divide the data into N number of calculation periods, count data transition frequencies for the N calculation periods, calculate dispersion values of the data transition frequencies for the N calculation periods, and output the control code corresponding to a largest dispersion value, in response to a counting interruption signal and a counting completion signal, wherein n is equal to or greater than 2, N is greater than n, and the data is divided to n number of unit intervals (UI), and wherein a phase shift of each of the calculation periods with respect to its corresponding UI is different from a phase shift of any of the other calculation periods with respect to its corresponding UI.

Data equalizing circuit and data equalizing method

A data equalizing circuit includes an equalizer configured to control a gain of data according to a value of a control code and output a controller gain; and a detection unit configured to divide n cycles of the data into N periods, count data transition frequencies for n/N periods while changing the value of the control code, calculate dispersion values of data transition frequencies for 1/N periods of the data from the data transition frequencies for the n/N periods, and finally output the value of the control code corresponding to a largest dispersion value, wherein n is equal to or greater than 2 and is set such that boundaries of the respective n/N periods of the data have different positions in the 1 UI data.

Growing community of inventors

Icheon-si, South Korea

Chun Seok Jeong