Novatek Microelectronics Corp.

Chun-Po Huang

Soon-Jyh Chang

Che-Yi Lin

Chien-Chung Chen

Liang-Ting Kuo

Po-Yao Ko

Yi-Shen Cheng

Chia-Chuan Lee

Hsu-Yu Huang

A low voltage differential signaling receiver includes a resistor load pair, an input stage, a current mode logic stage and a comparator circuit. The input stage includes a P-type transistor pair and a N-type transistor pair. The P-type transistor pair and the N-type transistor pair are configured to generate first differential output voltages on the resistor load pair according to differential input signals. The current mode logic stage is configured to enhance a gain of the first differential output voltages into second differential output voltages. The latch circuit is configured to generate third differential output voltages according to the second differential output voltages and latch the third differential output voltages. The comparator circuit is configured to compare the third differential output voltages and generate a single-ended output signal.

Low voltage differential signaling receiver

A successive approximation register (SAR) analog to digital converter (ADC) and a method of detecting an offset of a comparator are introduced. The SAR ADC includes a switch circuit, a comparator and a calibration circuit. The switch circuit is configured to perform a swapping operation on a first intermediate analog signal and a second intermediate analog signal to generate a first swapped analog signal and a second swapped analog signal. The comparator is coupled to the switching circuit and is configured to compare the first intermediate analog signal and the second intermediate analog signal before the swapping operation to generate a least-significant-bit value. The comparator is further configured to compare the first swapped analog signal and the second swapped analog signal after the swapping operation to generate a calibration bit value. The calibration circuit is configured to determine whether the comparator has an offset according to the least-significant-bit value and the calibration bit value.

Successive approximation register analog to digital converter and offset detection method thereof

A data receiver for a double data rate (DDR) memory includes a first stage circuit and a second stage circuit. The first stage circuit is deployed for receiving a single-ended signal from the DDR memory and converting the single-ended signal into a pair of differential signals. The second stage circuit, coupled to the first stage circuit, is deployed for receiving the differential signals from the first stage circuit and converting the differential signals into an output signal. Both of the first stage circuit and the second stage circuit are implemented in a core voltage domain.

Data receiver and controller for DDR memory

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Tainan, Taiwan

Chun-Po Huang