Au Optronics Corporation

Mediatek Corporation

Powerchip Semiconductor Corporation

Chun-Nan Lin

Wen-Ching Tsai

Kuo-Yuan Tu

Po-Lin Chen

Shu-Feng Wu

Hao-Lin Chiu

Yih-Chyun Kao

Chia-Ming Chang

Yung-Chun Lei

Po-Liang Yeh

Shine-Kai Tseng

Shuo-Hong Wang

Shu-Wei Tsao

Chia-Tsung Wu

Chi-Ting Kuo

Ko-Jui Lee

Chia-Hung Li

Ming-Yu Liu

Yu-Min Lin

Wen-Yi Wu

Chih-Yuan Lin

Jyh-Shin Pan

Tai-Tso Lin

Chen-Yuan Tu

Chun-Hao Su

Jiang-Jin You

Chia Wen Dai

Chi-Jui Lin

Cho-Ching Ko

Chao-Yu Yang

Shih-Che Huang

Li-Kai Chen

Chia-Ping Yang

Shu-Yin Yang

An electronic device and a manufacturing method thereof are provided. The electronic device includes an array substrate, which includes a substrate, a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer. The substrate has a substrate surface. The first conductive layer is located on the substrate surface. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer and includes a first sputtering layer, a second sputtering layer, and a third sputtering layer. The second insulating layer is located on the second conductive layer. The second sputtering layer is located between the first and third sputtering layers, and includes a first metal element. The first sputtering layer includes the first metal element and a second metal element. The third sputtering layer includes the first metal element and a third metal element.

Electronic device and manufacturing method thereof

A metal structure includes a patterned molybdenum tantalum oxide layer and a patterned metal layer. The patterned molybdenum tantalum oxide layer is disposed on a first substrate, in which the patterned molybdenum tantalum oxide layer includes about 2 to 12 atomic percent of tantalum. Both of an atomic percent of molybdenum and an atomic percent of oxygen of the patterned molybdenum tantalum oxide layer are greater than the atomic percent of tantalum of the patterned molybdenum tantalum oxide layer. The patterned metal layer is disposed on the patterned molybdenum tantalum oxide layer.

Metal structure and method for fabricating same and display panel using same

A fabrication method of a pixel structure and a pixel structure are provided. A first patterned metal layer including scan lines and a gate is formed on a substrate. A first insulation layer, a semiconductor layer, an etching stop pattern and a metal layer are formed sequentially on the first patterned metal layer. The metal layer and the semiconductor layer are patterned to form a second patterned metal layer and a patterned semiconductor layer. The second patterned metal layer includes data lines, a source and a drain. The patterned semiconductor layer includes a first semiconductor pattern completely overlapping the second patterned metal layer and a second semiconductor pattern without overlapping the second patterned metal layer, wherein the second semiconductor pattern includes a channel pattern and a marginal pattern. The channel pattern is between the source and the drain and the marginal pattern surrounds the first semiconductor pattern.

Pixel structure and fabricating method thereof

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate, a channel layer, a gate insulation layer, a source, a drain and a silicon-aluminum-oxide layer. The gate is disposed on a substrate. The channel layer is disposed on the substrate. The channel layer overlaps the gate. The gate insulation layer is disposed between the gate and the channel layer. The source and the drain are disposed on two sides of the channel layer. The silicon-aluminum-oxide layer is disposed on the substrate and covers the source, the drain and the channel layer.

Semiconductor device and manufacturing method thereof

A thin-film transistor (TFT) includes a gate electrode, a gate dielectric layer, a semiconductor layer, source/drain electrodes, a passivation layer and a protection layer. The gate electrode is disposed on a substrate. The gate dielectric layer covers the gate electrode and the substrate. The semiconductor layer is disposed on the gate dielectric layer and above the gate electrode. The semiconductor layer has a channel region disposed above the gate electrode and source/drain regions disposed at both sides of the channel region. The source/drain electrodes are disposed on the source/drain regions of the semiconductor layer and each has a barrier layer disposed on the source/drain regions of the semiconductor layer and a conductive layer disposed on the barrier layer. The passivation layer is disposed over the surface of the source/drain electrodes. The protection layer is disposed over the substrate, the passivation layer, and the channel region of the semiconductor layer.

Thin film transistor and method for manufacturing thereof

An active device including a source, a drain, an oxide semiconductor layer, a gate and a gate insulator layer is provided. The source includes first stripe electrodes parallel to each other and a first connection electrode connected thereto. The drain includes second stripe electrodes parallel to each other and a second connection electrode connected thereto, wherein the first stripe electrodes and the second stripe electrodes are parallel to each other, electrically isolated, and alternately arranged, and a zigzag trench is formed therebetween. The gate extends along the zigzag trench. The oxide semiconductor layer is in contact with the source and drain, wherein a contact area among the oxide semiconductor layer and each first stripe electrodes substantially equals to a layout area of each first stripe electrodes and a contact area among each second stripe electrodes substantially equals to a layout area of each second stripe electrodes.

Active device

An active device, a driving circuit structure, and a display panel are provided. The active device includes a gate, a gate insulation layer covering the gate, a semiconductor layer disposed above the gate, an etching stop layer disposed on the gate insulation layer and the semiconductor layer, a source, and a drain. The gate forms a meandering pattern on a substrate. The semiconductor layer has an area substantially defining a device region where the active device is. The etching stop layer has a first contact opening and a second contact opening. The first contact opening and the second contact opening separated from each other and both exposing the semiconductor layer. The source and the drain separated from each other are disposed on the etching stop layer and in contact with the semiconductor layer through the first contact opening and the second contact opening, respectively.

Active device, driving circuit structure, and display panel

A semiconductor device structure on a substrate and a manufacture method thereof is provided. The semiconductor device structure includes an oxide semiconductor transistor and a passivation layer containing free hydrogen. The semiconductor device structure is formed by following steps. A gate electrode is formed on the substrate. A gate dielectric layer covers the gate electrode. A source electrode is formed on the gate dielectric layer. A drain electrode is formed on the gate dielectric layer and separated from the source electrode and thereby forming a channel distance. An oxide semiconductor layer is formed on the gate dielectric layer, the source electrode and the drain electrode and between the source electrode and the drain electrode. The oxide semiconductor layer is further electrically connected with the source electrode and the drain electrode. A passivation layer covers the oxide semiconductor layer, the source electrode and the drain electrode. The passivation layer has a groove formed therein, and the groove surrounds the oxide semiconductor layer.

Semiconductor device structure and method for manufacturing the same

An active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5&#xb0; to about 30&#xb0;.

Active device array substrate

A pixel structure disposed on a substrate including a thin film transistor (TFT), a bottom capacitor electrode, a dielectric layer, an upper capacitor electrode, a passivation layer, and a pixel electrode is provided. The TFT having a source/drain and the bottom capacitor electrode are disposed on the substrate. The dielectric layer is disposed on the bottom capacitor electrode. The upper capacitor electrode has a semiconductor layer, a barrier layer, and a metal layer. The semiconductor layer is disposed on the dielectric layer above the bottom capacitor electrode. The barrier layer is disposed on the semiconductor layer. The metal layer whose material includes copper, a copper alloy, or a combination thereof is disposed on the barrier layer. The passivation layer covers the TFT and the upper capacitor electrode and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening.

Pixel structure, display panel, eletro-optical apparatus, and method thererof

A display panel structure having a circuit element disposed thereon and method of manufacture are provided. The display panel includes a substrate and the circuit element disposed on the substrate. The circuit element has a first interface layer and a first conductive layer. Both the first interface layer and the first conductive layer have cooper materials. The material which makes the first interface layer includes a reactant or a compound of the material which makes the first conductive layer. The method for manufacturing includes the following steps: forming a first interface layer on the substrate; forming a first conductive layer on the first interface layer; and etching the first conductive and interface layers to form a pattern. The existence of the first interface reduces the penetration of the first conductive layer on the substrate and improves the adhesive force between the first conductive layer and the substrate.

Display panel structure and manufacture method thereof

A display panel structure having a circuit element disposed thereon and method of manufacture are provided. The display panel includes a substrate and the circuit element disposed on the substrate. The circuit element has a first interface layer and a first conductive layer. Both the first interface layer and the first conductive layer have copper materials. The material which makes the first interface layer includes a reactant or a compound of the material which makes the first conductive layer. The method for manufacturing includes the following steps: forming a first interface layer on the substrate; forming a first conductive layer on the first interface layer; and etching the first conductive and interface layers to form a pattern. The existence of the first interface reduces the penetration of the first conductive layer on the substrate and improves the adhesive force between the first conductive layer and the substrate.

A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.

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Hsin-Chu, Taiwan

Chun-Nan Lin