Qualcomm Mems Technologies, Inc.

Sandisk Technologies Inc.

Hitachi Global Storage Technologies Netherlands B.v.

Sandisk 3d LLC

Chun-Ming Wang

Masaaki Higashitani

Kim Yang Lee

Teruo Sasagawa

Yung-Tin Chen

Chenche Huang

Chen-Che Huang

Fan Zhong

Stephen Zee

Clarence Chui

Jeffrey Brian Sampsell

Manish Kothari

Suryaprakash Ganti

Ming-Hau Tung

Howard Gordon Zolla

Steven Patrick Maxwell

Quang Le

Tsann Lin

Gang Xu

Steven J Radigan

Lior Kogut

Tsung Yuan Chen

David Patrick Druist

Surya Prakash Ganti

Jeffrey Lan

Chengbin Qiu

Roy E Scheuerlein

Mustafa Pinarbasi

Johann Alsmeier

Christopher John Petti

George Matamis

James Mac Freitag

Edward Hin Pong Lee

Tong Zhang

Ion Bita

Jui-lung Li

Bing K Yen

Jixin Yu

Yuki Mizutani

Jih-Shiuan Luo

David Eugene Heim

Marie-Claire Cyrille

Masayuki Hiroi

Daxin Mao

Zhenyu Lu

Yuji Takahashi

Kota Funayama

Paul Wai Kie Poon

Qi Luo

Hiroaki Koketsu

Vincent Shih

Makoto Yoshida

Chengbin Qui

Lauren Matsumoto

A device structure includes an array of semiconductor devices located in an array region over a substrate, metal lines laterally extending from the device region to a peripheral interconnection region, and interconnect via structures located in the peripheral interconnection region, and contacting a portion of a respective one of the plurality of metal lines. The metal lines include a first metal line and a second metal line each having a serpentine region which contacts a respective interconnect via structure.

Interconnects containing serpentine line structures for three-dimensional memory devices and methods of making the same

A method of dividing drain select gate electrodes in a three-dimensional vertical memory device is provided. An alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.

Self-aligned isolation dielectric structures for a three-dimensional memory device

A structure is formed on a substrate, which includes a stack of alternating layers comprising insulating layers and electrically conductive layers and a plurality of memory stack structures extending through the stack. At least one bridge line structure is formed on top surfaces of a respective subset of the plurality of memory stack structures to provide local lateral electrical connection. At least one dielectric material layer is formed over the at least one bridge line structure and the plurality of memory stack structures. A plurality contact via structures is formed through the dielectric material layer. The plurality of contact via structures includes at least one first contact via structure contacting a top surface of a respective bridge line structure, and second contact via structures contacting a top surface of a respective memory stack structure.

Bridge line structure for bit line connection in a three-dimensional semiconductor device

A lithography mask includes a plurality of patterning features formed on a mask substrate and a first plurality of sub-resolution assist features (SRAFs) formed substantially perpendicular to the patterning features on the mask substrate.

Method of patterning NAND strings using perpendicular SRAF

A photolithography mask including a plurality of mask features. Adjacent mask features are separated by a gap and are offset from each other such that individual mask features have one-side dense portions and two-side dense portions. Also a photolithography method that includes a step of providing a substantially opaque mask having N stepped rows of offset, substantially transparent, rectangular mask features, where N is an integer and N&#x2267;2. The method also includes illuminating a photoresist layer located over an underlying material with dipole illumination through the substantially transparent, rectangular mask features in the substantially opaque mask to form 2N rows of exposed regions in the photoresist layer. The exposed regions have a substantially elliptical or substantially circular shape when viewed from above the photoresist layer.

Method and mask for enhancing the resolution of patterning 2-row holes

MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One embodiment provides a method of making a MEMS device that includes depositing a polymer layer over a substrate, forming an electrically conductive layer over the polymer layer, and vaporizing at least a portion of the polymer layer to form a cavity between the substrate and the electrically conductive layer. Another embodiment provides a method for making an interferometric modulator that includes providing a substrate, depositing a first electrically conductive material over at least a portion of the substrate, depositing a sacrificial material over at least a portion of the first electrically conductive material, depositing an insulator over the substrate and adjacent to the sacrificial material to form a support structure, and depositing a second electrically conductive material over at least a portion of the sacrificial material, the sacrificial material being removable by heat-vaporization to thereby form a cavity between the first electrically conductive layer and the second electrically conductive layer.

Method of creating MEMS device cavities by a non-etching process

Bit line connections for non-volatile storage devices and methods for fabricating the same are disclosed. At least two different types of bit line connections may be used between memory cells and bit lines. The different types of bit line connections may be structurally different from each other as follows. One type of bit line connection may include a metal pad between an upper via and lower via. Another type of bit line connection may include an upper via and lower via, but does not include the metal pad. Three rows of bit line connections may be used to relax the pitch. For example, two rows of bit line connections on the outside may have the metal pad, whereas bit line connections in the middle row do not have the metal pad.

Bit-line connections for non-volatile storage

Embodiments of MEMS devices include support structures having substantially vertical sidewalls. Certain support structures are formed through deposition of self-planarizing materials or via a plating process. Other support structures are formed via a spacer etch. Other MEMS devices include support structures at least partially underlying a movable layer, where the portions of the support structures underlying the movable layer include a convex sidewall. In further embodiments, a portion of the support structure extends through an aperture in the movable layer and over at least a portion of the movable layer.

MEMS devices having support structures with substantially vertical sidewalls and methods for fabricating the same

A photomask for exposure of a semiconductor wafer using dipole illumination and method of manufacturing the same is disclosed. A method of forming a pattern on a semiconductor using the photomask is also disclosed. The photomask may have an array of islands that are used for printing lines using dipole illumination. The photomask may have sub-resolution assist features (SRAF) to assist in printing the lines. The SRAF may include an array of holes.

Photomask with assist features

A microelectromechanical systems device having support structures formed of sacrificial material surrounded by a protective material. The microelectromechanical systems device includes a substrate having an electrode formed thereon. Another electrode is separated from the first electrode by a cavity and forms a movable layer, which is supported by support structures formed of a sacrificial material.

Support structure for MEMS device and methods therefor

A method of making a device includes forming a first hard mask layer over an underlying layer, forming first features over the first hard mask layer, forming a first spacer layer over the first features, etching the first spacer layer to form a first spacer pattern and to expose top of the first features, removing the first features, patterning the first hard mask using the first spacer pattern as a mask to form first hard mask features, removing the first spacer pattern. The method also includes forming second features over the first hard mask features, forming a second spacer layer over the second features, etching the second spacer layer to form a second spacer pattern and to expose top of the second features, removing the second features, etching the first hard mask features using the second spacer pattern as a mask to form second hard mask features, and etching at least part of the underlying layer using the second hard mask features as a mask.

Method of making pillars using photoresist spacer mask

A method of making a device includes forming an underlying mask layer over an underlying layer, forming a first mask layer over the underlying mask layer, patterning the first mask layer to form first mask features, undercutting the underlying mask layer to form underlying mask features using the first mask features as a mask, removing the first mask features, and patterning the underlying layer using at least the underlying mask features as a mask.

Method of making sub-resolution pillar structures using undercutting technique

One embodiment of the invention provides a method of forming a plurality of contact holes, including forming a first feature and a second feature over an underlying material, forming sidewall spacers on the first and second features, removing the first and second features without removing the sidewall spacers, forming a cover mask at least partially exposing the sidewall spacers, and etching the underlying material using the cover mask and the sidewall spacers as a mask to form the plurality of contact holes.

Method of forming contact hole arrays using a hybrid spacer technique

Growing community of inventors

Fremont, CA, United States of America

Chun-Ming Wang