Mediatek Corporation

Industrial Technology Research Institute

Realtek Semiconductor Inc.

Chun-Ming Kuo

Ho-Chi Huang

Shih-Chi Shen

I-Ping Chang

Chi-Yeh Yu

Chi-Hsueh Wang

Ying-Ying Chen

YingYing Chen

Shih-Kung Chang

Song-Yu Yang

Chii-Horng Chen

Tai-Yuan Yu

Shao-Wei Feng

JengYi Tsai

Chun-Chi Chen

Jiann-Ching Guey

Pei-Kai Liao

Chien-Hwa Hwang

Ang-Sheng Lin

Ping-Hung Chiang

Shin-Lin Shieh

Hui-Huang Chang

Yen-Hui Yeh

Keng-Jan Hsiao

Wen-Chi Chao

Sheng-Hua Yang

Hung-Shiun Fu

Wei-nan Sun

Ai-Hsuan Liu

Tso-Mo Chen

Shin-Yi Lin

Chia-Feng Lin

Yen-Ping Lin

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The configuration specifies a bundle size N. Modulation symbols in N consecutive PRBs are precoded with a same precoder. The UE determines whether a precoding condition is true. The precoding condition is that modulation symbols in a first set of resources and a second set of resources are precoded with a same precoder. Each set of the first set of resources and the second set of resources contains N PRBs. When the precoding condition is met: the UE measures reference signals in the second set of resources; the UE determines a channel condition of the first set of resources in consideration of the measurements of the reference signals in the second set of resources.

Inter-bundle channel estimation and synchronization for downlink data reception

A method of providing over-the-air assistance information for interference cancellation or suppression to the receiver is proposed. Under a first solution, a two-stage DCI (downlink control information) or SCI (sidelink control information) scheduling method is proposed. The set of first-stage DCI or SCI provides a part of scheduling information which is beneficial for interference cancellation or suppression and is broadcasted by a transmitter or scheduler to all receivers. The set of second-stage DCI or SCI includes the remaining scheduling information and is unicasted by a transmitter or scheduler to each receiver. Under a second solution, assistance information DCI for interference cancellation or suppression is broadcasted by a transmitter or scheduler to all receivers.

Over-the-air signal assisted interference cancellation or suppression

A frequency-generating circuit includes a frequency synthesizer circuit and a controller. The frequency synthesizer circuit generates a radio-frequency clock signal according to a reference clock signal and a channel number. The controller is coupled to the frequency synthesizer circuit, generates a power-down control signal for controlling at least a portion of the frequency synthesizer circuit to power down. The frequency synthesizer circuit includes an accumulator for generating an accumulated value according to the channel number. The frequency synthesizer circuit generates the radio-frequency clock signal according to the reference clock signal and the accumulated value. The controller maintains the accumulated value of the accumulator when the portion of the frequency synthesizer circuit powers down.

Methods for controlling a frequency synthesizer circuit and a frequency-generating circuit utilizing the same

A frequency-generating circuit includes a frequency synthesizer circuit and a reference clock signal processor. The frequency synthesizer circuit receives a processed reference clock signal and generates a radio-frequency clock signal according to the processed reference clock signal. The reference clock signal processor receives an original reference clock signal from an oscillator and processes the original reference clock signal according to an indication signal to generate the processed reference clock signal. The indication signal is generated according to a required reference clock frequency of a communications apparatus. When the required reference clock frequency is high, a frequency of the processed reference clock signal is a multiple of a frequency of the original reference clock signal, and when the required reference clock frequency is low, the frequency of the original reference clock signal is a multiple of the frequency of the processed reference clock signal.

Frequency-generating circuit and communications apparatus

An embodiment of the invention provides a method to be performed by a first wireless communication apparatus in communicating with a second wireless communication apparatus. First, the first wireless communication apparatus determines whether a plurality of sub-channels are simultaneously available for the second wireless communication apparatus. Then, the first wireless communication apparatus simultaneously uses the sub-channels to transmit a plurality of divergent copies of a data segment to the second wireless communication apparatus, respectively, if the sub-channels are simultaneously available for the second wireless communication apparatus.

Wireless communication apparatuses and related methods

A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.

Frequency synthesizer with injection pulling/pushing suppression/mitigation and related frequency synthesizing method thereof

A frequency synthesizer includes a digitally controlled oscillator, a sigma-delta modulation circuit and a controller. The digitally controlled oscillator is arranged to generate an oscillating clock. The sigma-delta modulation circuit is arranged to generate an SDM input to the digitally controlled oscillator. The controller is arranged to adjust an operating frequency of the SDM circuit in response to a transmit power level of a transmitter using the oscillating clock.

Frequency synthesizer and related method for improving power efficiency

A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one resistance-capacitance (RC) detection result, wherein the digital compensation filter includes an RC compensation module; and tuning the digital compensation filter by inputting the RC detection result into the RC compensation module. For example, the RC detection result may correspond to a detected value representing a product of a resistance value and a capacitance value. In another example, the at least one RC detection result may be obtained by performing RC detection on at least a portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein. An associated digital compensation filter and an associated calibration circuit are also provided.

Method for tuning a digital compensation filter within a transmitter, and associated digital compensation filter

A clock generator utilized for providing a clock signal includes: a first oscillator and a switching circuit. The switching circuit is coupled to the first oscillator and a second oscillator, and utilized for receiving a first oscillating signal generated from the first oscillator and a second oscillating signal generated from the second oscillator, and selecting one of the first oscillating signal and the second oscillating signal as the clock signal according to a status signal.

Clock generator and method of generating clock signal

A clock generator for a mobile device, capable of operating in one of a full-power mode and a low-power mode according to a standby signal to generate a high-frequency clock signal and a low-frequency clock signal is disclosed. The clock generator includes a crystal oscillator, for generating an oscillation signal of a specific frequency according to the power mode of the clock generator; a frequency division block, for dividing the oscillation signal by a specific divisor according to the power mode of the clock generator to generate the low-frequency clock signal; and a buffer block, for amplifying the oscillation signal to generate the high-frequency clock signal; wherein during each power mode, a frequency of the low-frequency clock signal is substantially the same.

Clock generator with frequency error compensation and mobile device using the same

The invention provides a method for frequency offset estimation according to a filtered signal with destroyed phase information. In one embodiment, a filter filters an original signal according to a series of first filter coefficients to obtain a first-channel component of the filtered signal, and filters the original signal according to a series of second filter coefficients to obtain a second-channel component of the filtered signal. A series of third filter coefficients are first derived from the first filter coefficients. The original signal is then filtered according to the third filter coefficients to obtain a reference signal. A first frequency offset value is estimated according to the first-channel component of the filtered signal and the reference signal, wherein the first-channel component of the filtered signal is a first-channel component of an artificial signal, and the reference signal is a second-channel component of the artificial signal.

Method for frequency offset estimation and automatic frequency control for filtered signal with destroyed phase information and signal transceiver

A dummy burst detection method. The method begins with generating a dummy burst nominal power &#x3b7;of a received burst and a normal burst nominal power &#x3b7;of the received burst, wherein the dummy burst nominal power &#x3b7;is generated based on the hypotheses that the received burst is a dummy burst, and the normal burst nominal power &#x3b7;is formed based on the hypotheses that the received burst is a normal burst. A likelihood of the received burst is determined according to the dummy burst nominal power &#x3b7;, the normal burst nominal power &#x3b7;, and the noise power of the received burst.

Dummy burst detecting method and apparatus

A mobile device capable of scaling input data and a method thereof. The mobile device comprises a data segmentation module, a quality measure module, and a scaling module. The data segmentation module divides the input data into a plurality of subdata. The quality measure module, coupled to the data segmentation module, calculates signal quality of each subdata. The scaling module, coupled to the quality measure module, scales each subdata according to corresponding signal quality.

Method of scaling input data and mobile device utilizing the same

A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one loop gain calibration result by performing loop gain calibration based upon signals of at least a portion of the transmitter, and obtaining at least one resistance-capacitance (RC) detection result by performing RC detection on the portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein, wherein the RC detection result corresponds to a detected value representing a product of a resistance value and a capacitance value, and the digital compensation filter includes a gain compensation module and an RC compensation module; and tuning the digital compensation filter by respectively inputting the loop gain calibration result and the RC detection result into the gain compensation module and the RC compensation module. An associated digital compensation filter and an associated calibration circuit are also provided.

Growing community of inventors

Taipei County, Taiwan

Chun-Ming Kuo