Mediatek Corporation

Myson Technology Inc.

Realtek Semiconductor Inc.

Chun-Ming Chou

Yu-Tien Chang

Lin-Ming Hsu

Chien-Wen Chen

Ming-Hui Tung

Chung-Yu Lin

Tsen-Shau Yang

Tsung-Yen Liu

Wen-Jung Su

Tsen-Shun Yang

Jia-Der Hsieh

Shaoyong Duan

Kuo-Ho Tsai

A system on chip includes a dynamic random access memory (DRAM) controller, a secure range (SR) permission checker, a plurality of intellectual property (IP) cores. The DRAM controller includes a SR table configured to store a start address, an end address, and enabled registers of each SR and an access identification (AID) permission table configured to store access permissions of SRs of each AID. The SR permission checker is embedded in the DRAM controller or a bus and linked to the SR table and the AID permission table, and configured to check the access permissions of the SRs according to the AID permission table. The plurality of IP cores linked to the DRAM controller, and comprising a translation lookaside buffer (TLB) comprising an input-output memory management unit (IOMMU) table or an input-output memory protection unit (IOMPU) table to store SR information.

Input-output memory management unit with memory protection

The invention provides method and system for improving efficiency of protecting multi-content process. The system may cooperate with a memory, and may comprise one or more hardware IPs (intellectual properties) for content processing, one of the one or more IPs may be associated with multiple access identities. The memory may comprise multiple different ranges, each range may register an access of one of the multiple access identities as a permissible access. The method may comprise: selecting one of the access identities for processing a first content, and using the selected access identity when said IP accesses the memory during processing of the first content; selecting a different one of the access identities for processing a second content, and using the selected different access identity when said IP accesses the memory during processing of the second content.

Method and system for improving the efficiency of protecting a multi-content process

A video device, a wireless audio device and a method for performing audio and video (AV) synchronization between the video device and the wireless audio device are provided. The method includes: utilizing a controller of the video device to determine a video delay of the video device; utilizing the controller to determine an audio delay of the video device; utilizing the controller to receive information of a communications quality of the wireless audio device from the wireless audio device, to determine a wireless communications delay between the video device and the wireless audio device according to the communications quality; utilizing the controller to generate a time map information according to the video delay, the audio delay and the wireless communications delay; and transmitting the time map information from the video device to the wireless audio device for AV synchronization between the video device and the wireless audio device.

Video device, wireless audio device and method for performing audio and video synchronization between video device and wireless audio device

The present invention discloses a circuit capable of protecting low-voltage devices. The circuit includes: a pin configured to receive a signal of an external device; a control voltage generating circuit configured to generate a first control voltage according to a supply voltage to turn on a protected device when the supply voltage is at a high level, and generate a second control voltage according to a voltage of the pin to turn on the protected device when the supply voltage is at a low level; and the protected device configured to be turned on according to one of the first and the second control voltages and thereby electrically couple the pin with an internal circuit, in which the difference between the voltage of the pin and each of the first and the second control voltages is within a maximum withstanding voltage of the protected device.

Circuit capable of protecting low-voltage devices

The object of the present invention is to provide a clock synthesizer IC which can produce clock signals with much lower radiated EMI. The clock synthesizer IC comprises: a forward programmable counter for dividing the frequency of input clock signals by M; a feedback programmable counter for dividing the frequency of input clock signals by N; a phase-frequency detector for accepting one input signal from said forward programmable counter and another from said feedback programmable counter, outputting two signals whose levels are determined by phase difference of said two input signals; a loop filter accepting the output signal of said phase-frequency detector and outputting a signal with high-frequency component filtered out; a voltage-controlled oscillator accepting the output signal of said loop filter and outputting a signal as the input signal of said feedback programmable counter and as the output signal of the whole clock synthesizer whose frequency is determined by input voltage; a programmable logic array, for controlling the dividing-number M and N of said forward programmable counter and said feedback programmable counter respectively. An up/down counter for controlling the dividing-number N of said feedback programmable counter in cooperation with said programmable logic array by way of dividing the binary representation of said dividing-number D.sub.n D.sub.(n-1) . . . D.sub.1 D.sub.0 into two groups: D.sub.n . . . D.sub.k and D.sub.(k-1) . . . D.sub.0 and controlling them by said programmable logic array and said up/down counter respectively in which the time interval of transition of D.sub.n D.sub.(n-1) . . . D.sub.1 D.sub.0 is determined by said up/down counter.

Clock synthesizer for low EMI applications

A waveform shaping circuit includes an input terminal, an output terminal, and a plurality of cascaded circuit stages. Each of the cascaded circuit stages includes a delay circuit having an output and an input, a current source, and a switch circuit, connected electrically to the output of the delay circuit and controlled by the delay circuit, for connecting electrically the current source to the output terminal. The input of the delay circuit of a first one of the circuit stages is connected electrically to the input terminal. The input of the delay circuit of remaining ones of the circuit stages is connected electrically to the output of the delay circuit of an immediately preceding one of the circuit stages. The delay circuits have equal delay times. The total delay time provided by the delay circuits of the circuit stages is equal to or is a multiple of half a bit time of the fundamental data rate. The current sources have current values derived from time samples of a finite impulse response of a filter transfer function of the waveform shaping circuit.

Growing community of inventors

Hsinchu, Taiwan

Chun-Ming Chou