Silicon Storage Technology, Inc.

Mstar Semiconductor, Inc.

Mitac International Corporation

Nanning Fugui Precision Industrial Co., Ltd.

Ali Corporation

A Plus Biotechnology Company Limited

Environmental Protection Administration, R.o.c.

Chun-Ming Chen

Jeng-Wei Yang

Man-Tang Wu

Chien-Sheng Su

Nhan Do

Hieu Van Tran

Dana Lee

Bomy A Chen

Xian Liu

Feng Zhou

Changyuan Chen

Mandana Tadayoni

Chih-Ching Wu

Kai-Hsing Wu

I-Hsing Chen

Yu-Ling Chiu

Fu-Chieh Chang

Hsiang Wei Lo

Ping Sheng Yu

Felix (Ying-Kit) Tsui

Wei-Chou Hung

Hsuan-Ting Lai

Yu-Yun Hsieh

Chun-Chun Lin

Chen-Chih Fan

Chiao-Ying Wu

Chu An Luo

Yu-Chieh Wu

Shyh-Wei Chen

The present invention provides a surgery device for osteotomy comprises a first body component, a second body component. The first body component has a side guide edge and an upper guide edge for forming a cutting track. The second body component has a lower guide edge disposed below the upper guide edge. A guide groove is formed between the upper guide edge and the lower guide edge for guiding the saw blade to cut. The upper guide edge has a first correcting perforation. The lower guide edge has a second correcting perforation. There is a regulative angle between a first hole axis of the first correcting perforation and a second hole axis of the second correcting perforation. Compared to the prior art, the present invention can improve the efficiency and accuracy of the surgery.

Surgery device for osteotomy

A method for sorting unsystematic environment risk of underground storage tank systems includes: generating an unsystematic environmental site assessment priority list for the underground storage tank systems using a risk weight assessment module based on facility level factor data and operational status factor data of each underground storage tank system; obtaining an actual soil gas detection data for each underground storage tank system after conducting an environmental site assessment on the priority list; and generating an investigation list according to the contamination potential assessment result of each underground storage tank system using a contamination potential assessment module based on the actual soil gas detection data as a basis for subsequent investigation and regulation on the underground storage tank systems.

Method for sorting unsystematic environment risk of underground storage tank systems

A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.

Non-volatile split gate memory cells with integrated high K metal control gates and method of making same

A method of forming a memory device with memory cells in a memory area, and logic devices in first and second peripheral areas. The memory cells each include a floating gate, a word line gate and an erase gate, and each logic device includes a gate. The oxide under the word line gate is formed separately from a tunnel oxide between the floating and erase gates, and is also the gate oxide in the first peripheral area. The word line gates, erase gates and gates in both peripheral areas are formed from the same polysilicon layer. The oxide between the erase gate and a source region is thicker than the tunnel oxide, which is thicker than the oxide under the word line gate.

Method of manufacturing a split-gate flash memory cell with erase gate

A non-volatile memory cell includes a semiconductor substrate of first conductivity type, first and second spaced-apart regions in the substrate of second conductivity type, with a channel region in the substrate therebetween. A floating gate has a first portion disposed vertically over a first portion of the channel region, and a second portion disposed vertically over the first region. The floating gate includes a sloping upper surface that terminates with one or more sharp edges. An erase gate is disposed vertically over the floating gate with the one or more sharp edges facing the erase gate. A control gate has a first portion disposed laterally adjacent to the floating gate, and vertically over the first region. A select gate has a first portion disposed vertically over a second portion of the channel region, and laterally adjacent to the floating gate.

Split-gate flash memory cell with improved scaling using enhanced lateral control gate to floating gate coupling

A multimedia control method, which includes following parts. A first program preview request for a specified program channel is received from a set-top box. Multiple video clips are acquired according to the first program preview request and the multiple video clips are divided into at least a first video clip group and a second video clip group with sequence number. A first multicast channel is set for the first video clip group, and a second multicast channel is set for the second video clip group. The first video clip group is sent to the set-top box using the first multicast channel, and the second video clip group is sent to the set-top box using the second multicast channel.

Multimedia control method and server

A method of forming a non-volatile memory cell includes forming spaced apart first and second regions in a substrate, defining a channel region there between. A floating gate is formed over a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region. A tunnel oxide layer is formed around the sharp edge. An erase gate is formed over the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer. A word line gate is formed over a second portion of the channel region which is adjacent to the second region. The forming of the word line gate is performed after the forming of the tunnel oxide layer and the erase gate.

Method of forming flash memory with separate wordline and erase gates

A method of forming a memory device with memory cells over a planar substrate surface and FinFET logic devices over fin shaped substrate surface portions, including forming a protective layer over previously formed floating gates, erase gates, word line poly and source regions in a memory cell portion of the substrate, then forming fins into the surface of the substrate and forming logic gates along the fins in a logic portion of the substrate, then removing the protective layer and completing formation of word line gates from the word line poly and drain regions in the memory cell portion of the substrate.

Method of integrating FinFET CMOS devices with embedded nonvolatile memory cells

A method of forming a memory device that includes forming a first insulation layer on a semiconductor substrate, forming a conductive material layer on the first insulation layer, forming an insulation block on the conductive material layer, forming an insulation spacer along a side surface of the insulation block and on the conductive material layer, etching the conductive material layer to form a block of the conductive material disposed directly under the insulation block and the insulation spacer, removing the insulation spacer, forming a second insulation layer having a first portion wrapping around an exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer over the substrate, and forming a conductive block insulated from the block of the conductive material by the second insulation layer and from the substrate by the first and second insulation layers.

Method of forming low height split gate memory cells

A non-volatile memory cell, and method of making, that includes a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

Method of making split gate non-volatile memory cell with 3D FinFET structure

A memory device and method including a semiconductor substrate with memory and logic device areas. A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.

Integration of split gate flash memory array and logic devices

A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between, and a conductive floating gate disposed over a first portion of the channel region and a first portion of the source region. An erase gate includes a first portion that is laterally adjacent to the floating gate and over the source region, and a second portion that extends up and over the floating gate. A conductive word line gate is disposed over a second portion of the channel region. The word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate. The thickness of insulation separating the word line gate from the second portion of the channel region is less than that of insulation separating the floating gate from the erase gate.

Split gate non-volatile memory cell having a floating gate, word line, erase gate, and method of manufacturing

A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.

Method of forming self-aligned split-gate memory cell array with metal gates and logic devices

A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

Split gate non-volatile memory cell with 3D finFET structure, and method of making same

A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area, forming a first conductive layer over and insulated from the substrate, forming a first insulation layer on the first conductive layer and removing it from the memory and HV areas, performing a conductive material deposition to thicken the first conductive layer in the memory and HV areas, and to form a second conductive layer on the first insulation layer in the LV area, performing an etch to thin the first conductive layer in the memory and HV areas and to remove the second conductive layer in the LV area, removing the first insulation layer from the LV area, and patterning the first conductive layer to form blocks of the first conductive layer in the memory, LV and HV areas.

Growing community of inventors

Taipei, Taiwan

Chun-Ming Chen