Macronix International Co., Ltd.

Chun-Min Cheng

Jung-Yi Guo

Erh-Kun Lai

Ming-Tsung Wu

Chun-Ling Chiang

Yen-Hao Shih

Shih-Ping Hong

Yu-Chung Chen

Ling-Wu Yang

Han-Hui Hsu

Chien-Lan Chiu

Kuang-Hao Chiang

Pei-Ci Jhang

Chih-Yuan Wu

Jr-Meng Wang

Kuanf-Wen Liu

A semiconductor structure includes a substrate, a common source plane disposed on the substrate, a plurality of memory cells vertically disposed on the substrate and electrically connected to the common source plane, a common source line disposed on the substrate and electrically connected to the common source plane, and an isolation pillar. The common source line extends along a first direction and has a first segment and a second segment. The isolation pillar interposes the first segment and the second segment of the common source line.

Semiconductor structure and method of fabricating the same

A three-dimensional memory device includes a plurality of conductive layers and insulating layers alternately formed to define a multi-layer stacked structure on a first region of a semiconductor substrate. The multi-layer stacked structure includes a stair structure and a non-stair structure. A plurality of memory structures are located in the non-stair structure to form a memory array region, and each memory structure passes through the conductive layers and the insulating layers. A plurality of bow-height adjustment features are located in a second region of the semiconductor substrate.

Three dimensional memory device

A memory device and manufacturing method thereof are provided. The memory device includes a pair of stacked structures, a charge storage layer, and a channel layer. The stacked structures are disposed on a substrate. Each stacked structure includes gate layers and insulating layers stacked alternately, and a cap layer on the gate layers and the insulating layers. The charge storage layer is disposed on sidewalls of the stacked structures facing each other. The channel layer covers the charge storage layer, and has a top portion, a body portion, and a bottom portion. The top portion covers sidewalls of the cap layers of the stacked structures. The bottom portion covers a portion of the substrate located between the stacked structures. The body portion is connected between the top and bottom portions. Dopant concentrations of the top and bottom portions are respectively greater than a dopant concentration of the body portion.

Memory device and manufacturing method thereof

A process for fabricating a 3D memory is shown. Linear stacks, each of which includes alternately stacked gate lines and insulating layers, are formed. A charge trapping layer is formed covering the linear stacks. An amorphous semiconductor layer is formed on the charge trapping layer. An ultra-thin cap layer is formed on the amorphous semiconductor layer. The amorphous semiconductor layer is annealed to form a crystalline channel layer, wherein agglomeration of the material of the amorphous semiconductor layer is suppressed by then ultra-thin cap layer.

Process for fabricating 3D memory

A method of forming a three-dimensional memory device is provided. Insulating layers and sacrificial layers are stacked alternatively on a substrate. At least one first opening is formed through the insulating layers and the sacrificial layers. Protection layers are formed on surfaces of the sacrificial layers exposed by the sidewall of the first opening. A charge storage layer is formed on the sidewall of the first opening and covers the protection layers. A channel layer is formed on the charge storage layer. The sacrificial layers and the protection layers are replaced with electrode layers. A three-dimensional memory device is further provided.

Three-dimensional memory device and method of forming the same

A semiconductor structure for three-dimensional memory device and a manufacturing method thereof are provided. The semiconductor structure is disposed on the substrate and has a plurality of openings penetrating through the semiconductor structure and extending into the substrate. The semiconductor structure includes a substrate, a stacked structure and an epitaxial layer. The stacked structure includes insulating layers and gate layers stacked alternatively. Each of the plurality of openings includes a first portion located above the surface of the substrate and a second portion located below the surface of the substrate. The aspect ratio of the second portion is more than 1. The epitaxial layer is disposed in each of the plurality of openings. The top surface of the epitaxial layer is between the top surface and the bottom surface of the i-th insulating layer as counted upward from the substrate, wherein i&#x2265;2.

Semiconductor structure and manufacturing method thereof

3D memory structure

Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. The methods may include two or more nitride removal steps during formation of gate layers in vertical memory cells. The two or more nitride removal steps may allow for wider gate layers increasing the gate fill-in, reducing the occurrence of voids, and thereby improving the word line resistance.

Methods of manufacturing semiconductor devices with improved metal gate fill-in for vertical memory cell and devices thereof

A method for forming a semiconductor structure is provided. The method includes following steps. First, a stack of alternate conductive layers and insulating layers is formed on a buffer layer on a buried layer. Next, a first opening is formed through the stack and through a portion of the buffer layer. Thereafter, a spacer is formed on a sidewall of the first opening.

Method for forming a semiconductor structure

A method of fabricating a semiconductor device, including the following steps. A plurality of fin structures are formed on a substrate. There is a trench between the fin structures. At least two times of circulating processes are performed. The circulating processes include: a deposition process and an etching process. The deposition process is performed to fill a first conductor material layer in the trench. The first conductor material layer covers top parts and sidewalls of the fin structures. The etching process is performed to remove a part of the first conductor material layer.

Semiconductor device and method of fabricating the same

A method of manufacturing a semiconductor device is provided. Gate structures are formed on a substrate, and a first dielectric layer having grooves is formed between two adjacent gate structures. An upper surface of the first dielectric layer is lower than an upper surface of the gate structures. Afterwards, an intermediate layer is formed to cover the gate structures, the first dielectric layer, and the grooves, and openings are formed therein. Each opening is formed between two adjacent gate structures, and the first dielectric layer is removed through the opening. Next, a second dielectric layer is formed on the intermediate layer, so as to define an air gap between two adjacent gate structures. Furthermore, a semiconductor device is provided.

Semiconductor memory array with air gaps between adjacent gate structures and method of manufacturing the same

Present example embodiments relate generally to methods of fabricating a semiconductor device, and semiconductor devices thereof, comprising providing a substrate, forming an insulating base layer on the substrate, and disposing a conductive layer on the insulating base layer at an initial temperature. The methods further comprise increasing the initial temperature at a first increase rate to a first increased temperature and performing an in-situ annealing process to the conductive layer at the first increased temperature. The methods further comprise increasing the first increased temperature at a second increase rate to a second increased temperature, and forming an insulating layer after performing the in-situ annealing process at the second increased temperature.

Semiconductor device including multi-layer structure

Present example embodiments relate generally to semiconductor devices and methods of fabricating a semiconductor device comprising forming an insulating base layer over a surface of a substrate. The method further comprises forming a multilayer over the insulating base layer, the multilayer having conducting and insulating layers. The method further comprises etching a pattern in the multilayer and forming a charge storage layer over the patterned multilayer. The method further comprises forming a protective silicon layer over the charge storage layer, followed by performing a heat treatment process.

Method for filling polysilicon gate in semiconductor devices, and semiconductor devices

An apparatus of and method for making a semiconductor structure having a shallow trench isolation (STI) trench with a substantially v-shaped profile, that is the distance between top portions is greater than the distance between bottom portions of shallow trench isolation (STI) structure sidewalls adjacent to the trench, provides for substantially seamless and substantially void-free gate structures. The semiconductor structures are formed by implanting an implantation species into the sidewalls, which allows for the top portions of the sidewalls to be etched away at a greater rate than that of the bottom portions, resulting in the substantially v-shaped profile. And the substantially v-shaped profile allows for subsequent device layers to more easily and smoothly fill in the v-shaped trenches, due to a wider opening toward the tops of the trenches.

Semiconductor device formation

A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.

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Hsinchu, Taiwan

Chun-Min Cheng