Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun-Mei Lee

Chia-Hsiang Chen

Li-Kong Turn

Chih-Chien Hung

Han-Ming Sheng

Hsiang-Chung Liu

Ming-Huei Tseng

De-Ming Liang

A frame layout and method for determining the overlay accuracy of a first chip image relative to a second chip image when the first and second chip images are used to form a single chip. One embodiment employs a vernier scale in two orthoginal directions included in the scribeline of both the first chip image and the second chip image. Another embodiment employs a box in box pattern included in the scribeline of both the first chip image and the second chip image. A layer of photoresist on an integrated circuit wafer is exposed with the first and second chip image and the associated monitor images. When the photoresist is developed the overlay accuracy of the first chip image relative to the second chip image can be determined directly from the monitor images in the photoresist.

Frame layout to monitor overlay performance of chip composed of multi-exposure images

Growing community of inventors

Chu-Dung, Taiwan

Chun-Mei Lee