Winbond Electronics Corporation

Information Storage Devices, Inc.

Windbond Electronics Corp.

Aptix Corporation

Chun-Mai Liu

Albert V Kordesch

Kung-Yen Su

Hagop A Nazarian

Ming-Bing Chang

Paul Vande Voorde

Hieu Van Tran

Wei-Fan Chen

Ralph G Whitten

Lawrence D Engh

Len-Yi Leu

James Brennan, Jr

Yu-Lin Lee

Alan Elbert Comer

Anthony Dunne

Peter Holzmann

Kaiman Chan

Geoff Jackson

Scott Graham

Michael David La Fleur

Kai-Man Chan

Ken Su

Ping Guo

Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range &#x2212;40 C to +85 C. Furthermore, the temperature variation at room temperature (&#x2dc;25 C) can be reduced to nearly zero.

Semiconductor diffused resistors with optimized temperature dependence

An impedance network. The network includes a plurality of impedance elements, at least one end terminal, and a wiper terminal. The network also includes a first plurality of switching elements selectively providing tap positions to the at least one end terminal, selectable at a first specified increment of impedance elements in the plurality of impedance elements. The network further includes a second plurality of switching elements selectively providing a tap positions to the wiper terminal, selectable at a second specified increment of impedance elements in the plurality of impedance elements.

Variable impedance network with coarse and fine controls

A method of forming a semiconductor memory having rows and columns of memory cells is as follows; forming a plurality of rows of program gate lines from a second layer polysilicon; forming a plurality of rows of select gate lines from a third polysilicon layer; forming a plurality of rows of diffusion source lines: forming a plurality of local bitlines from a first layer metal, the cells along each column being divided into a pre-designated number of groups, and drains of the cells in each group being connected to a local bitline extending across the cells in the group of cells; and forming a plurality of global bitlines from a second layer metal extending along every two columns of cells, each global bitline being configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.

Method of forming memory arrays based on a triple-polysilicon source-side injection non-volatile memory cell

Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range &minus;40 C to &plus;85 C. Furthermore, the temperature variation at room temperature (&tilde;25 C) can be reduced to nearly zero.

Method of forming semiconductor diffused resistors with optimized temperature dependence

A field oxide device (FOD) useful for electrostatic discharge (ESD) protection and other applications. The FOD is characterized as being capable of achieving a relatively low breakdown voltage and capable of handling relatively high currents during an ESD event. In general, the FOD includes a zener junction to promote an earlier breakdown of the device. The zener junction also provides a planar-like breakdown region which makes it capable of handling relatively high currents. In particular, the FOD includes a p-doped substrate having a drain-side n&plus; diffusion region and a source-side n&plus; diffusion region which are separated by a field oxide. The FOD further includes a p&plus; doped region that interfaces with the drain-side n&plus; diffusion region to form a zener junction. The breakdown voltage of the FOD can be easily set by controlling the doping concentration and energy of the p&plus; doped region. The FOD may additionally include one or more n&plus; regions at the respective boundaries of the drain-side and source-side n&plus; diffusion regions to provide improved junction curvature. In addition to the field oxide interposed between the drain-side and source-side n&plus; diffusion regions, field oxides can be added respectively at the drain and source ends to provide isolation from other devices within an integrated circuit.

Field oxide device with zener junction for electrostatic discharge (ESD) protection and other applications

A semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The cells along each column are divided into a predesignated number of groups, and the drain regions of the cells in each group are connected to a local bitline extending across the cells in the group of cells. A global bitline extends along every two columns of cells, and is configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells. The floating gate of each cell is from a first layer polysilicon, the program gate lines are from a second polysilicon layer, the select gate lines are from a third polysilicon layer, and the source lines are diffusion lines.

Memory array architectures based on a triple-polysilicon source-side injection non-volatile memory cell

A method for fabricating a triple self-aligned non-volatile memory device is disclosed. The method includes forming isolation oxide on a substrate. A plurality of floating gates are formed by depositing and self-aligning a first polysilicon layer to the isolation oxide. A common source area is then defined on the substrate between the floating gates. A second polysilicon layer is deposited over the common source area and self-aligned with respect to the isolation oxide. A third polysilicon layer is deposited adjacent to the plurality of floating gates. A plurality of select gates are then formed by self-aligning the third polysilicon layer to the isolation oxide. Furthermore, at least one drain area is defined on the substrate.

Method of making triple self-aligned split-gate non-volatile memory device

A silicon controlled rectifier (SCR) serving as an electrostatic discharge (ESD) protection device having a vertical zener junction for triggering breakdown. The SCR includes a p-doped substrate having an n-doped well, spaced-apart p and n doped regions for cathode connection formed within the n-doped well, and spaced-apart p and n doped regions for anode connection formed with the p-substrate external to the n-doped well. The SCR further includes a vertical zener junction situated between the anode n doped region and the n-well. The vertical zener junction has a p doped region sandwiched between two n doped regions. The n doped region of the vertical zener junction closest to the n-well may extend at least partially within the n-well, or be totally outside of the n-well. The SCR may further include respective field oxides between the anode p and n doped regions, between the anode n doped region and the vertical zener junction, and between the vertical zener junction and the n-doped well. Also provided is an n-doped substrate version of the SCR. The SCR with the vertical zener junction is characterized as having a relatively low breakdown voltage, having improved current handling capability for more reliable and robust operations, and having a breakdown voltage dependent on the doping concentration of the lighter doped p or n doped region of the vertical zener junction.

Vertical zener-triggered SCR structure for ESD protection in integrated circuits

A method of forming a capacitor on a substrate includes forming a first polysilicon layer overlying the substrate to define a floating gate. A second polysilicon overlying the first polysilicon layer is formed to define a control gate and a first electrode of the capacitor. A dielectric layer is formed over the second polysilicon layer. A third polysilicon layer is formed over the dielectric layer. The third polysilicon layer is etched to define a second electrode of the capacitor. Thereafter the dielectric layer is etched.

Capacitor fabrication process for analog flash memory devices

Adaptive programming method and apparatus for flash memory analog storage. The present invention method is to adjust the voltage of the programming pulse each time based on the result of the previous pulse. The expected change in the programmed value is compared to the measured change, and the difference used to improve the model of that cell after each programming pulse. The algorithm is &ldquo;adaptive&rdquo; because the voltage of each pulse is adapted to whatever the cell needs. If the cell is programming too slowly, the voltage is increased dramatically to make it faster. Conversely if the results show that a particular cell is programming too fast, the next voltage pulse is increased by only a small amount (or even decreased if necessary). Because the response of the cell is non-linear, a special analog circuit is used to calculate the optimum voltage for each pulse. As one alternative, a digital calculation may also be used to program the cells. Because of the programming speed of the exemplary method, a voice signal may be sampled and stored in flash memory one cell at a time. Variable programming parameters other than voltage may be used if desired.

Adaptive programming method and apparatus for flash memory analog storage

An analog recording and playback system using non-volatile flash memory. An array of flash memory cells is used to store an analog signal and retrieve the stored analog signal on a real-time basis. A plurality of column driver circuits are coupled to the columns of flash memory cells for simultaneous programming and reading. A programming algorithm is used to write the analog signal within an operating range of the flash memory cells since the operating range may shift due to process variations. The system includes trimbit circuits to provide a trimmable initial programming voltage, programming step, programming current, read current, and select gate voltage. The system further includes a Serial Peripheral Interface ('SPI') that interfaces with a host microcontroller. The host microcontroller can send a number of commands to the system through the SPI for efficient message management. These commands include the basic commands to record or playback and various addressing and message cueing options. The system utilizes row and column redundancy to increase production yield.

Recording and playback integrated system for analog non-volatile flash

A two-terminal fuse-antifuse structure comprises a horizontal B-fuse portion and a vertical A-fuse portion disposed between two metallization layers of an integrated circuit device. The two-terminal fuse-antifuse can be programmed with a relatively high current applied across the two terminals to blow the B-fuse, or with a high voltage applied across the two terminals to program the A-fuse. Such a device, connected between two circuit nodes, initially does not provide an electrical connection between the two circuit nodes. It may then be programmed with a relatively high voltage to blow the A-fuse, causing it to conduct between the two circuit nodes. Then, upon application of a relatively high current between the two circuit nodes, the B-fuse will blow, making the device permanently non-conductive. An improvement permitting higher current programming of B-fuses either alone or as part of Ab-fuse structures, incorporates an air gap which provides a pocket of space either above, below or both above and below the B-fuse portion of the device. This air gap provides a place for material disrupted (melted or vaporized) by a fuse or Ab-fuse programming event to go, eliminates direct contact between the dielectric material and the fuse-portion of the device, and also thermally isolates the melted fuse material from the dielectric, thus reducing the physical stress within the dielectric itself associated with high current programming and avoiding undesired collateral damage normally associated with high current programming events. The creation of an air gap around the fuse neck is accomplished by the removal of a sacrificial layer of an oxidizable polymer material in a gaseous and/or plasma state through a small hole in the dielectric referred to as a sacrificial via opening or just 'sacrificial via'. After removal of the oxidizable polymer material through the sacrificial via, the sacrificial via is sealed with a passivation layer formed of a polymeric material to prevent damage to the underlying structure. The integration of the air gap and sacrificial via sealing into the current fuse process manufacturing requires the following additional processing steps: (1) Air gap definition; (2) Air gap evacuation with oxygen plasma; (3) the application of the sealing polymer; and (4) the curing of the sealing polymer.

Growing community of inventors

San Jose, CA, United States of America

Chun-Mai Liu