United Microelectronics Corp.

Other

United Silicon Incorporated

Chun-Lung Chen

Kun-Yuan Liao

Chia-Lin Lu

Feng-Yi Chang

Wei-Hao Huang

Chih-Sen Huang

Chieh-Te Chen

Hsuan-Hsu Chen

Hsi-Mao Hsiao

Ching-Wen Hung

Yu-Cheng Tung

Hui-Lin Wang

Bin-Siang Tsai

Chen-Yi Weng

Jing-Yin Jhang

Yu-Tsung Lai

Chin-Yang Hsieh

Fu-Yu Tsai

Kun-Ju Li

Tai-Cheng Hou

Chih-Yueh Li

Wei-Xin Gao

Yi-Wei Chen

En-Chiuan Liou

Shih-Fang Tzou

Zhen Wu

Kun-Chen Ho

Hsi-Chin Lin

Shi-Xiong Lin

Chien-Ting Lin

Chun-Hsien Lin

Chung-Yi Chiu

Lung-En Kuo

Chuan-Chang Wu

Chih-Wei Kuo

Shih-Chieh Hsu

Ching-Ling Lin

Chia-Fu Hsu

Hsiao-Pang Chou

Chun-Mao Chiou

Yi-Wei Tseng

Jian-Cun Ke

Shang-Yuan Tsai

Hsiang-Hung Peng

Wen-Hua Cheng

Wen-Wen Zhang

Ming-Chou Lu

Kai-Teng Cheng

Pei-Jou Lee

Tzung-Han Lee

Jiunn-Hsiung Liao

Yi-Hui Lee

Chih-Wei Yang

Jia-Rong Wu

Ying-Cheng Liu

Ying-Chih Lin

Tong-Hsin Lee

Chia-Hsun Tseng

Ching-Pin Hsu

Dien-Yang Lu

Chung Yi Chiu

Yi-Kuan Wu

Yu-Ting Hung

Chia-Fu Yeh

Chia-Wei Hsu

Wen-Shan Wei

H C Yu

Shun-Yu Huang

Cheng-Hsing Chuang

Hung-Chen Yu

Jung-Huang Chen

Hong-Chen Yu

Shin-Fa Lin

Yi-Xiang Chen

Liang Ju Wei

Yu-Sheng Chen

Chien-Lin Chen

A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate and a top electrode on the MTJ; forming a first inter-metal dielectric (IMD) layer around the MTJ and the top electrode; forming a stop layer on the first IMD layer; forming a second IMD layer on the stop layer; performing a first etching process to remove the second IMD layer and the stop layer; performing a second etching process to remove part of the top electrode; and forming a metal interconnection to connect to the top electrode.

Semiconductor device and method for fabricating the same

A control method of a multi-stage etching process and a processing device using the same are provided. The control method of the multi-stage etching process includes the following step S. A stack information of a plurality of hard mask layers is set. An etching target condition is set. Through a machine learning model, a parameter setting recipe of the hard mask layers is generated under the etching target condition. The machine learning model is trained based on the stack information of the hard mask layers, a plurality of process parameters and a process result.

Control method of multi-stage etching process and processing device using the same

A method of fabricating an MTJ device is provided including the following process. A first via is formed in the first dielectric layer. A first electrode layer is formed on the first dielectric layer and the first via. An MTJ stack layer is formed on the first electrode layer. A patterned second electrode layer is formed on the MTJ stack layer and used as a mask. A first ion beam etching process is performed to etch the patterned second electrode layer and pattern the MTJ stack layer and the first electrode layer to form a second electrode, an MTJ stack structure, and a first electrode. A first protective layer is formed to cover the second electrode and the MTJ stack structure. A second ion beam etching process is performed to remove a portion of the MTJ stack structure and a portion of the first electrode.

Method of fabricating magnetic tunneling junction device

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and form a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer on the CESL, forming a contact plug in the ILD layer and adjacent to the gate structure, forming a first stop layer on the ILD layer, and removing the first stop layer and the ILD layer around the gate structure to form an air gap exposing the CESL.

A magnetic memory including a substrate, a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ) stack, a first protection layer, and a second protection layer is provided. The SOT layer is located over the substrate. The MTJ stack is located on the SOT layer. The first protection layer and the second protection layer are located on the sidewall of the MTJ stack. The first protection layer is located between the second protection layer and the MTJ stack. There is a notch between the second protection layer and the SOT layer.

Magnetic memory and manufacturing method thereof

A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

A method for a clean procedure during manufacturing a semiconductor device, includes: providing a patterned sacrificial gate structure including a gate dielectric and a sacrificial layer; wherein the patterned sacrificial gate structure is embedded in a dielectric layer and an upper surface of the sacrificial layer is exposed; performing a first etching process to remove the sacrificial layer; and performing a hydrophilic treatment and a hydrophobic treatment to remove a residue of the sacrificial layer.

Method for clean procedure during manufacturing semiconductor device

A method of cutting fins includes the following steps. A photomask including a snake-shape pattern is provided. A photoresist layer is formed over fins on a substrate. A photoresist pattern in the photoresist layer corresponding to the snake-shape pattern is formed by exposing and developing. The fins are cut by transferring the photoresist pattern and etching cut parts of the fins.

Method of cutting fin

A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

Magnetoresistive random access memory (MRAM) device

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

Method of manufacturing magnetoresistive random access memory (MRAM) device

A manufacturing method of a semiconductor device includes the following steps. First patterned structures are formed on a substrate. Each of the first patterned structures includes a first semiconductor pattern and a first bottom protection pattern disposed between the first semiconductor pattern and the substrate. A first protection layer is formed on the first patterned structures and the substrate. A part of the first protection layer is located between the first patterned structures. A first opening is formed in the first protection layer between the first patterned structures. The first opening penetrates the first protection layer and exposes a part of the substrate. A first etching process is performed after forming the first opening. A part of the substrate under the first patterned structures is removed by the first etching process for suspending at least a part of each of the first patterned structures above the substrate.

Semiconductor device

Semiconductor device and manufacturing method thereof

Growing community of inventors

Tainan, Taiwan

Chun-Lung Chen