United Microelectronics Corp.

Chun-Ling Lin

Chi-Mao Hsu

Chin-Fu Lin

Tsun-Min Cheng

Ko-Wei Lin

Huei-Ru Tsai

Kuo-Chih Lai

Hsin-Yu Chen

Chun-Hung Chen

Shu Min Huang

Bor-Shyang Liao

Min-Chung Cheng

Yen-Liang Lu

Hung-Miao Lin

Ying-Lien Chen

Sheng-Yi Su

Yu-Ren Wang

Pin-Hong Chen

Chiu-Hsien Yeh

Po-Chun Chen

Chih-Hsun Lin

Chia Chang Hsu

Szu-Hao Lai

Te-Lin Sun

Jia-Jia Chen

Ching-Wei Hsu

Che-Nan Tsai

Chi-Ray Tsai

Bin-Siang Tsai

Chun-Yuan Wu

Yen-Chen Chen

Hsin-Fu Huang

Chia-Chang Hsu

Chun-Chieh Chiu

Ai-Sen Liu

Ching-Li Yang

Home-Been Cheng

Yang-Ju Lu

Yu-Han Tsai

Tsung-Hsun Tsai

Jen-Po Huang

Tzu-Hao Liu

Shu-Min Huang

Xu Yang Shen

Seng Wah Liau

Meng-Hong Tsai

A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.

High electron mobility transistor and method for forming the same

An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

Interconnect structure

An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.

Electrical chemical plating process

Interconnect structure and fabrication method thereof

A method is provided for forming copper material over a substrate. The method includes forming a barrier layer over a substrate. Then, a depositing-soaking-treatment (DST) process is performed over the barrier layer. A copper layer is formed on the cobalt layer. The DST process includes depositing a cobalt layer on the barrier layer. Then, the cobalt layer is soaked with Hgas at a first pressure. The cobalt layer is treated with a Hplasma at a second pressure. The second pressure is lower than the first pressure.

Method for forming copper material over substrate

A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.

Method for fabricating a MIM capacitor

A semiconductor process includes the following steps. A wafer on a pedestal is provided. The pedestal is lifted to approach a heating source and an etching process is performed on the wafer. An annealing process is performed on the wafer by the heating source. In another way, a wafer on a pedestal, and a heating source on a same side of the wafer as the pedestal are provided. An etching process is performed on the wafer by setting the temperature difference between the heating source and the pedestal larger than 180&#xb0; C.

Semiconductor process

A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.

Through silicon via (TSV) process

A method for fabricating a semiconductor device is provided. The method includes the following steps. Firstly, a substrate having a nitride layer and a platinum (Pt)-containing nickel (Ni)-semiconductor compound layer is provided. Then the nitride layer and the Pt are removed in situ with a chemical solution including a sulfuric acid component and a phosphoric acid component.

Method for fabricating semiconductor device

Through silicon via (TSV) structure and process thereof

A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure.

Semiconductor structure and fabrication method thereof

A method of processing a substrate is provided. The method includes: providing a substrate, wherein the substrate includes a silicon layer; etching the substrate to form a cavity; filling a first conductor in part of the cavity; performing a first thermal treatment on the first conductor; filling a second conductor in the cavity to fill-up the cavity; and performing a second thermal treatment on the first conductor and the second conductor.

Method of manufacturing semiconductor structure

The present invention provides a method for forming a salicide layer. First, a metal-atom-containing layer is formed on a substrate, a first rapid thermal process (RTP) is then performed to the metal-atom-containing layer to form a transitional salicide layer on a specific region. The metal-atom-containing layer is then removed, a thermal conductive layer is formed on the surface of the transitional salicide layer, and a second RTP is performed on the transitional salicide layer.

Method for forming a salicide layer

A manufacturing method for a semiconductor device having a metal gate includes providing a substrate having at least a first semiconductor device formed thereon, forming a first gate trench in the first semiconductor device, forming a first work function metal layer in the first gate trench, and performing a decoupled plasma oxidation to the first work function metal layer.

Manufacturing method for semiconductor device having metal gate

Growing community of inventors

Tainan, Taiwan

Chun-Ling Lin