Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun-Lin Tsai

Ru-Yi Su

Po-Chih Chen

Jiun-Lei Jerry Yu

Fu-Chih Yang

Chih-Chang Cheng

Ker Hsiao Huo

Yao-Chung Chang

Chien-Chih Chou

Jen-Hao Yeh

Tsung-Yi Huang

Kuo-Ming Wu

King-Yuen Wong

Wen-Chih Chiang

Yi-Min Chen

Shiuan-Jeng Lin

Jeng Gong

Puo-Yu Chiang

Yi-Cheng Chiu

Hung-Chou Lin

Karthick Murukesan

Chih-Yuan Chan

Chen-Chien Chang

Haw-Yun Wu

Chan-Hong Chern

Ruey-Hsin Liu

Yun-Hsiang Wang

Mark Chen

Chia-Hsun Wu

Jiun-Yu Chen

Kong-Beng Thei

Chun-Wei Hsu

Fu-Wei Yao

Denny Tang

Chen-Ju Yu

Chen-Bau Wu

Kuan-Lun Chang

Shih-Pang Chang

Shih-Chien Liu

Chih-Min Chiang

Tsyr Shyang

Chia-Jui Yu

Yen-Ku Lin

A semiconductor device includes a first semiconductor structure including a first high electron mobility transistor (HEMT) device, wherein the first HEMT device includes a first gate, a first source, and a first drain; and a second semiconductor structure stacked above and bonded to the first semiconductor structure, wherein the second semiconductor structure includes a second HEMT device and a third HEMT device, wherein the second HEMT device includes a second gate, a second source, and a second drain that is electrically connected to the first source, wherein the third HEMT device includes a third gate, a third source, and a third drain that is electrically connected to the first gate.

Wafer-on-wafer cascode HEMT device

Various embodiments of the present disclosure are directed towards a three-dimensional (3D) IC comprising semiconductor substrates with different bandgaps. The 3D IC chip comprises a first IC chip and a second IC chip overlying and bonded to the first IC chip. The first IC chip comprises a first semiconductor substrate with a first bandgap, and further comprises and a first device on and partially formed by the first semiconductor substrate. The second IC chip comprises a second semiconductor substrate with a second bandgap different than the first bandgap, and further comprises a second device on the second semiconductor substrate.

3D IC comprising semiconductor substrates with different bandgaps

Bonding a full-bridge device and an LLC device in a stack, or forming the full-bridge device and the LLC device on a same substrate, rather than connecting the devices, reduces a chip area associated with a power converter including the full-bridge device and the LLC device. Additionally, the full-bridge device and the LLC device consume less power because parasitic inductance and capacitance are reduced. Additionally, raw materials and production time are conserved that would otherwise have been used to connect the full-bridge device and the LLC device (e.g., via wires).

Forming integrated electronic devices for converting and downscaling alternating current

In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a stacked semiconductor substrate having a semiconductor material disposed over a base semiconductor substrate. The base semiconductor substrate has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. The stacked semiconductor substrate includes one or more sidewalls defining a crack stop ring trench that continuously extends in a closed path between a central region of the stacked semiconductor substrate and a peripheral region of the stacked semiconductor substrate surrounding the central region. The peripheral region of the stacked semiconductor substrate includes a plurality of cracks and the central region is substantially devoid of cracks.

Crack stop ring trench to prevent epitaxy crack propagation

The present disclosure relates an integrated chip. The integrated chip includes an isolation region disposed within a substrate and surrounding an active area. A gate structure is disposed over the substrate and has a base region and a gate extension finger protruding outward from a sidewall of the base region along a first direction to past opposing sides of the active area. A source contact is disposed within the active area and a drain contact is disposed within the active area and is separated from the source contact by the gate extension finger. A first plurality of conductive contacts are arranged on the gate structure and separated along the first direction. The first plurality of conductive contacts are separated by distances overlying the gate extension finger.

Device layout design for improving device performance

A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

Semiconductor device structure with high voltage device

The present disclosure provides a semiconductor device comprising a substrate; a first III-V compound layer over the substrate; a second III-V compound layer on the first III-V compound layer; a third III-V compound layer on the second III-V compound layer; a source region on the third III-V compound layer; a drain region on the third III-V compound layer; a first dielectric layer arranged on the second III-V compound layer through the third III-V compound layer; and a gate region on the first dielectric layer, wherein a bottom of the gate region is higher than a top surface of the first dielectric layer; the second lateral distance is larger than the first lateral distance.

HEMT device structure and manufacturing method thereof

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

Embedded JFETs for high voltage applications

The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer.

Semiconductor structure and manufacturing method thereof

Semiconductor structures including isolation regions and methods of forming the same are provided. A first layer is formed over a substrate, where the first layer comprises a semiconductor material. First and second trenches are etched, with each of the first and second trenches extending through the first layer and into the substrate. A wet etchant is introduced into the trenches, and the wet etchant etches a first opening below the first trench and a second opening below the second trench. Each of the first and second openings extends laterally below the first layer. The first and second openings are separated by a portion of the substrate adjoining the first and second openings. An oxidation process is performed to oxidize the portion of the substrate adjoining the first and second openings. An insulating material is deposited that fills the openings and the trenches.

Isolation regions for semiconductor structures and methods of forming the same

A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature.

Method of forming high electron mobility transistor

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Hsin-Chu, Taiwan

Chun-Lin Tsai