Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun Lin Tsai

Fu-Chih Yang

Jiun-Lei Jerry Yu

Ru-Yi Su

Chih-Chang Cheng

Fu-Wei Yao

Po-Chih Chen

Ruey-Hsin Liu

Ker Hsiao Huo

Chun-Wei Hsu

Ming-Cheng Lin

Yi-Min Chen

Man-Ho Kwan

Yun-Hsiang Wang

Chen-Ju Yu

Jen-Hao Yeh

King-Yuen Wong

Yi-Cheng Chiu

Yao-Chung Chang

Hung-Chou Lin

Karthick Murukesan

Kuo-Ming Wu

Wen-Chih Chiang

Shiuan-Jeng Lin

Alexander Kalnitsky

Ker-Hsiao Huo

Chih-Yuan Chan

Chen-Bau Wu

Yu-Syuan Lin

Haw-Yun Wu

Ting-Fu Chang

Kong-Beng Thei

Chan-Hong Chern

Hsiao-Chin Tuan

Chu Fu Chen

Liang-Yu Su

Mark Chen

Aurelien Gauthier Brun

Chih-Wen Yao

Chiu-Hua Chung

Chia-Ling Yeh

Chih-Wen Hsiung

Chen-Liang Chu

Yi-Sheng Chen

Alex Kalnitsky

Fei-Yuh Chen

Tysh-Bin Liu

Eric Huang

Ching Yu Chen

Shih-Kuang Hsiao

Fu Chin Yang

Wei Wang

Tien Sheng Lin

Tysh-Bin Lin

Chia-Chin Shen

Wei-Chen Yang

Kuei-Ming Chen

Chen-Chien Chang

Shih-Chien Liu

Chih-Wen (Albert) Yao

Sheng Yuan Lin

Ting Jia Hu

Chien Chih Chou

Fu Ji Yang

Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

Barrier structure configured to increase performance of III-V devices

In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer over a base substrate and an active layer over the channel layer. A source and a drain are over the active layer. A gate is over the active layer and laterally between the source and the drain. A dielectric is over the active layer and laterally surrounds the source, the drain, and the gate. A cap structure laterally contacts the source and is disposed laterally between the gate and the source. The source vertically extends to a top of the cap structure.

Cap structure coupled to source to reduce saturation current in HEMT device

The present disclosure relates to a transistor device. The transistor device includes a plurality of source contacts disposed over a substrate. A plurality of gate structures are disposed over the substrate. The plurality of gate structures wrap around one or more of the plurality of source contacts in one or more closed loops. A drain contact is disposed over the substrate. The drain contact continuously wraps around one or more of the plurality of gate structures as a continuous structure. The plurality of gate structures are separated from the drain contact by a first distance and are separated from a source contact of the plurality of source contacts by a second distance. The second distance is different than the first distance.

Ring transistor structure

In some embodiments, the present disclosure relates to a method of forming a transistor device. The method includes forming a source contact over a substrate, forming a drain contact over the substrate, and forming a gate contact material over the substrate. The gate contact material is patterned to define a gate structure that wraps around the source contact along a continuous and unbroken path.

Source leakage current suppression by source surrounding gate structure

Various embodiments of the present disclosure are directed towards an integrated chip including a first semiconductor layer overlying a substrate. A first barrier layer is disposed on the first semiconductor layer. A second semiconductor layer overlies and directly contacts the first barrier layer. A second barrier layer directly contacts the first barrier layer. A third semiconductor layer overlies the second barrier layer. A fourth semiconductor layer overlies the third semiconductor layer. Outer sidewalls of the third semiconductor layer, outer sidewalls of the fourth semiconductor layer, and outer sidewalls of the second barrier layer are respectively aligned.

Integration of p-channel and n-channel E-FET III-V devices with optimization of device performance

The transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer.

Method of forming a high electron mobility transistor

Various embodiments of the present disclosure are directed towards a two-dimensional carrier gas (2DCG) semiconductor device comprising an ohmic source/drain electrode with a plurality of protrusions separated by gaps and protruding from a bottom surface of the ohmic source/drain electrode. The ohmic source/drain electrode overlies a semiconductor film, and the protrusions extend from the bottom surface into the semiconductor film. Further, the ohmic source/drain electrode is separated from another ohmic source/drain electrode that also overlies the semiconductor film. The semiconductor film comprises a channel layer and a barrier layer that are vertically stacked and directly contact at a heterojunction. The channel layer accommodates a 2DCG that extends along the heterojunction and is ohmically coupled to the ohmic source/drain electrode and the other ohmic source/drain electrode. A gate electrode overlies the semiconductor film between the ohmic source/drain electrode and the other source/drain electrode.

Ohmic electrode for two-dimensional carrier gas (2DCG) semiconductor device

A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.

Semiconductor structure, HEMT structure and method of forming the same

In some embodiments, the present disclosure relates to a method of forming a high electron mobility transistor (HEMT) device. The method includes forming a passivation layer over a substrate. A source contact and a drain contact are formed within the passivation layer. A part of the passivation layer is removed to form a cavity. The cavity has a lower portion formed by a first sidewall and a second sidewall of the passivation layer and an upper portion formed by the first sidewall of the passivation layer and a sidewall of the source contact. A gate structure is formed within the passivation layer between the drain contact and the cavity. A cap structure is formed within the cavity.

A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

Semiconductor device having a plurality of III-V semiconductor layers

Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.

Front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV)

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.

Electrode structure for vertical group III-V device

Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

High voltage metal-oxide-semiconductor (HVMOS) device integrated with a high voltage junction termination (HVJT) device

A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.

Semiconductor structure and method for manufacturing thereof

In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.

Integration of p-channel and n-channel E-FET III-V devices without parasitic channels

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Hsin-Chu, Taiwan

Chun Lin Tsai