Macronix International Co., Ltd.

Chun-Lien Su

Ming-Shang Chen

Shuo-Nan Hung

Wenpin Lu

Chun-Chi Wang

Chun-Hsiung Hung

Chi-Yuan Chin

Wen-Pin Lu

Shaw-Hung Ku

Hung-Yu Chiu

Uway Tseng

Chi-Pei Lu

Sheng-Lun Wu

Yih-Shi Lin

Ying-Che Lo

Yin-Jen Chen

Shih-Keng Cho

Tsung-Hsien Wu

Hsin-Fu Lin

Hung-Chi Chen

Baw-Chyuan Lin

Zong-Qi Zhou

Ya-Jung Tsai

Kuei-Yun Chen

Systems, methods, and apparatus including computer-readable mediums for managing status information of logic units are provided. In one aspect, a device includes a semiconductor device including one or more logic units and a reporting bus and a controller coupled to the semiconductor device and configured to store status information of the one or more logic units in the semiconductor device. Each of the one or more logic units is configured to send information associated with the logic unit using a corresponding reporting unit in the semiconductor device through the reporting bus to the controller to indicate a status of the logic unit. The controller is configured to, in response to receiving the information associated with the logic unit, update corresponding status information of the logic unit based on the status of the logic unit.

Managing status information of logic units

Based on power on of an electronic device, a location of first data in a NAND flash memory of an electronic device is determined. The first data is transmitted to a shadow RAM of the electronic device, outputting the first data is output from the shadow RAM to a host device of the electronic device through a serial peripheral interface (SPI) when accessing the location of the first data in the NAND Flash memory.

Serial NAND flash with XIP capability

A method provides the capability to maintain integrity of a data image stored by computing a hash value ('digest') of the data image and comparing the hash value computed for the data image with a hash value computed for the data image and kept in a non-volatile area of memory. Bit flips in the data image that are a result of memory hardware errors reveal themselves as differences in the digest computed for the data image and the computed digest for the data.

Memory device having safety boot capability

A memory device includes a data register operatively coupled to the memory array, a cache operatively coupled to the data register, and an input/output interface operatively coupled to the cache. A controller executes a continuous page read operation to sequentially load pages to the data register and move the pages to the cache, in response to a page read command, executes the cache read operation in response to a cache read command to move data from the cache to the input/output interface, and to stall moving of the data from the cache until a next cache read command, and terminates the continuous page read operation in response to a terminate command.

Continuous read with multiple read commands

Serial NAND flash with XiP capability

A memory system stores user data including file content in clusters of memory space, folder entries, metadata, and a file allocation table FAT including FAT entries. The system comprises a cache memory, an addressable memory including memory space, and control logic coupled to the addressable memory and the cache memory. The control logic is configured to store user data in a current cluster at a current cluster offset including file content, and corresponding metadata including the current cluster offset, and a linked cluster offset of a linked cluster linking to the current cluster in the addressable memory, and to cache a FAT entry pointing to the current cluster in the cache memory.

File system management in memory device

A memory controller, which manages a memory device, receives a memory command. The memory controller determines whether the memory command is encrypted. Upon determining that the memory command is encrypted, the memory controller performs a decryption function corresponding to the memory command. Conditioned on the performance of the decryption function resulting in a successful decryption of the memory command, the memory controller performs an operation on a memory location corresponding to a memory address included in the memory command.

Secure memory

A memory device and a read method thereof are provided. The read method of the memory cell array includes: reading a memory cell array to obtain page data; dividing the page data into a plurality of chunk data; performing a first error correction operation on each of the chunk data in sequence to respectively generate a plurality of first corrected chunk data; performing a second error correction operation on the page data to generate corrected page data; and outputting the corrected chunk data by referring to an indicating signal.

Memory device and read method thereof

A flash memory system and a flash memory thereof are provided. The flash memory device includes a NAND flash memory and a control circuit. The NAND flash memory chip includes a cache memory, a page buffer; and an NAND flash memory array. The NAND flash memory array includes a plurality of pages, wherein each page includes a plurality of sub-pages, each sub-page has a sub-page length. The cache memory is composed of a plurality of sub cache and each sub cache corresponds to different pages of the NAND flash memory array. The page buffer is composed of a plurality of sub-page buffers and each sub-page buffer corresponds to different pages of the NAND flash memory array. The control circuit is coupled to the host and the NAND flash memory, and performs an access operation in units of one sub-page.

Flash memory system and flash memory device thereof

An input/output delay optimization method, used in an electronic system comprising a host controller and a memory device. The method comprising: switching the memory device from a first mode to a second mode a high power consumption mode of the memory device; transmitting one or more first read commands to the memory device, wherein the one or more first read commands are transmitted according to different output delay values; determining an optimized output delay value according to the response status of memory device for the one or more first read commands; transmitting one or more second read commands to the memory device, wherein the one or more second read commands are transmitted according to the optimized output delay value; receiving a known data from the memory device according to different input delay values; and determining an optimized input delay value according to the correctness of the received known data.

Input/output delay optimization method, electronic system and memory device using the same

A memory device, an electronic device, and associated read method are provided. The electronic device includes the memory device and a host device, which are electrically connected to each other. The memory device includes a NAND flash memory and a control logic. The NAND flash memory includes a first physical page, and the first physical page includes a plurality of first acquisition-units. The control logic is electrically connected to the NAND flash memory. The control logic receives a first-page address corresponding to the first physical page from a host device during a first page-read duration. Data stored at the plurality of first acquisition-units are respectively transferred to the host device during a second page-read duration.

Memory device, electronic device, and associated read method

A system includes a nonvolatile memory and a controller. The nonvolatile memory includes memory blocks. The controller is configured to perform at least one wear leveling operation, based on at least one degradation curve, to at least one of the plurality of memory blocks. Furthermore, a method associated with wear leveling is also disclosed herein.

Memory system and method capable of performing wear leveling

A memory device comprises, on an integrated circuit or multi-chip module, a memory including a plurality of memory blocks, a controller, and a refresh mapping table in non-volatile memory accessible by the controller. The controller is coupled to the memory to execute commands with addresses to access addressed memory blocks in the plurality of memory blocks. The refresh mapping table has one or more entries, an entry in the refresh mapping table mapping of an address identifying an addressed memory block set for refresh to a backup block address. The controller is responsive to a refresh command sequence with a refresh block address to execute a refresh operation, and is configured to restore mapping of the refresh block address to the backup block address upon power-on of the device, to scan the refresh mapping table for a set entry, and to register the set entry in the refresh mapping table.

In-place refresh operation in flash memory

A non-volatile register is provided. The non-volatile register includes a plurality of cell strings with respect to a plurality of bit lines, wherein each cell string includes a plurality of cells. Each word line is respectively connecting to a gate of one cell for each cell string to correspondingly form a page. The pages are configured into: a central page used as a register to store registered data; and a plurality of dummy pages at both sides of the central page. The dummy pages are controlled to provide a boosted channel voltage to a portion of memory cells of the central page, not being programmed. A source selection transistor is connected to a first side for each cell string. A drain selection transistor is connected to a second side for each cell string.

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Taichung, Taiwan

Chun-Lien Su