Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun-Liang Tai

Kuo-Bin Huang

Chun-Hsiang Fan

Ming-Hsi Yeh

Yu-Lien Huang

Chia-Pin Lin

Chun-Hung Lee

De-Fang Chen

Sheng-Hsiung Wang

Fan-Yi Hsu

Bi-Ming Yen

Chia-Cheng Tai

Wang-Hua Lin

Ta-Wei Lin

Shih-Hsiang Chiu

Chieh-Chun Chiang

A method of manufacturing a semiconductor device is provided. The method comprises the following steps of forming a first semiconductor layer over a substrate, the first semiconductor layer comprising a first semiconductor material; etching the first semiconductor layer to form a first recess; forming a second semiconductor layer in the first recess, the second semiconductor layer comprising a second semiconductor material different from the first semiconductor material; etching the first semiconductor layer and the second semiconductor layer to form a first fin comprising the second semiconductor layer and the first semiconductor layer; forming an insulation material over the substrate, wherein a top surface of the insulation material is flush with a top surface of the first fin; performing an implantation process on the first fin to form an implant region near the top surface of the first fin; and partially removing the insulation material to form shallow trench isolation regions, wherein the first fin is sandwiched by two adjacent shallow trench isolation regions.

Semiconductor device and manufacturing method thereof

A method for cleaning a semiconductor wafer is provided. The method includes placing a semiconductor wafer over a supporter arranged around a central axis of a spin base. The method further includes securing the semiconductor wafer using a clamping member positioned on the supporter. The movement of the semiconductor wafer during the placement of the semiconductor wafer over the supporter is guided by a guiding member located over the clamping member. The method also includes spinning the semiconductor wafer by rotating the spin base about the central axis. In addition, the method includes dispensing a processing liquid over the semiconductor wafer.

Method for cleaning semiconductor wafer

A method of processing a semiconductor substrate is provided. The semiconductor substrate may be placed on a spin chuck with a plurality of holding members, each holding member including a pin having a sloped portion to provide a gap between an upper edge of the substrate and the pin. Thereafter, one or more treatment fluids may be dispensed over the substrate.

Substrate vapor drying apparatus and method

Semiconductor wafer cleaning apparatus and method for cleaning semiconductor wafer

A semiconductor structure includes a substrate and a fin. The fin extends from the substrate and is formed with a hole therethrough. The hole is defined by a confronting pair of wall parts. One of the wall parts is more arcuate than the other of the wall parts. A method for fabricating the semiconductor structure is also disclosed.

Method of manufacturing a horizontal gate-all-around transistor having a fin

Systems and methods are provided for forming features through photolithography. A polymer layer is formed over a substrate. The polymer layer is patterned to form a first feature and a second feature, the first feature and the second feature being separated at a first distance. A rinse material is applied to the polymer layer including the first feature and the second feature. The rinse material is removed from the polymer layer including the first feature and the second feature to cause the first feature and the second feature to come into contact with each other. A third feature is formed based on the first feature and the second feature being in contact with each other.

Multi-line width pattern created using photolithography

A semiconductor device which includes a first gate structure on a substrate and a second gate structure on the substrate is provided. The semiconductor device further includes an inter-level dielectric (ILD) layer on the substrate between the first gate structure and the second gate structure, wherein a top portion of the ILD layer has a different etch selectivity than a bottom portion of the ILD layer.

Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure

The embodiments of methods and structures disclosed herein provide mechanisms of performing doping an inter-level dielectric film, ILD, surrounding the gate structures with a dopant to reduce its etch rates during the processes of removing dummy gate electrode layer and/or gate dielectric layer for replacement gate technologies. The ILDfilm may be doped with a plasma doping process (PLAD) or an ion beam process. Post doping anneal is optional.

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Hsinchu, Taiwan

Chun-Liang Tai