Mediatek Corporation

Powerchip Semiconductor Manufacturing Corporation

Novatek Microelectronics Corp.

Jmicron Technology Corp.

Chun-Liang Chen

Chien-Chih Lin

Tien-Chang Chang

Hann-Jye Hsu

You-Ming Tsao

Wen-Hsuan Lin

Yu-Cheng Lo

Yi-Le Yang

Chen-Chia Lee

The present disclosure provides a semiconductor package including a substrate, a display unit, a flexible substrate, a driving circuit, and a memory. The substrate has a first surface and a second surface opposite to each other, and the first surface has a display region and a bonding region. The display unit is disposed on the display region of the first surface. The flexible substrate is disposed below the second surface and has a connection portion extended to the bonding region of the first surface. The driving circuit is disposed on the flexible substrate and electrically connects with the display unit. The memory is disposed on the flexible substrate and electrically connects with the driving circuit.

Semiconductor package

The present disclosure provides a semiconductor package including a substrate, a display unit, a driving circuit, and at least one of memory. The substrate has a display region and a peripheral region. The display unit is disposed in the display region and electrically connects with the display unit. The memory is disposed in the peripheral region and electrically connected with the driving circuit. The driving circuit and the memory are spaced apart from each other.

A pad structure is formed on an IC die and includes a first conductive layer, a dielectric layer, a second conductive layer and a passivation layer. The first conductive layer is formed on an upper surface of the IC die and having a hollow portion. The dielectric layer covers the first conductive layer. The second conductive layer is formed on the dielectric layer and electrically connected to the first conductive layer. The passivation layer covers the second conductive layer and has an opening exposing the second conductive layer for receiving a bonding wire.

Pad structure and integrated circuit die using the same

An electronic device includes a memory controller and a processor. The memory controller controls access of a memory device. The processor performs a calibration operation to find a first setting range of a memory controller parameter under a first clock frequency of the memory device, to find a second setting range of the memory controller parameter under a second clock frequency of the memory device, and to determine a calibrated setting of the memory controller parameter according to an overlapped range of the first setting range and the second setting range.

Apparatus and method for controlling controllable clock source to generate clock signal with frequency transition

The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed in a second metal layer and directly under the metal pad, wherein an oxide layer is positioned between the first metal layer and the second metal layer.

Semiconductor device allowing metal layer routing formed directly under metal pad

A calibration method includes transmitting first data comprising a calibration data and a first checksum to the storage device according to each of a plurality of training parameter sets; recording a plurality of error indicators respectively which are corresponding to the plurality of training parameter sets and from the storage device; and identifying one of the plurality of training parameter sets as a predetermined parameter set according to the plurality of error indicators respectively corresponding to the plurality of training parameter sets; wherein each error indicator indicates whether transmitting the first data according to the corresponded training parameter set is successful.

Storage device calibration methods and controlling device using the same

A semiconductor device may include a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device and is directly contacting the first metal layer. The first specific metal layer routing is formed on a second metal layer of the semiconductor device and under the metal pad. In addition, the semiconductor device may include at least one via plug for connecting the first specific metal layer routing to at least one metal region in the first metal layer, where the aforementioned at least one via plug is formed directly under the metal pad.

The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing and a second specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing and the second specific metal layer routing are formed in a second metal layer of the semiconductor device, wherein the first specific metal layer routing is directly under the metal pad and the second specific metal layer routing is not directly positioned under the metal pad.

The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed on a second metal layer of the semiconductor device, and directly under the metal pad.

A USB device with a clock calibration function and a method for calibrating reference clocks of a USB device are provided. A USB 2.0 initial calibration is performed on the USB device in order to control an embedded oscillator (EMOSC) of the USB device to output a first reference clock compliance USB 2.0 specification and USB 3.0 specification during the initialization phase. After that, a USB 3.0 on-line calibration is performed on the USB device in order to control the EMOSC of the USB device to calibrate a second reference clock during a super-speed mode of USB 3.0 specification.

Generating reference clocks in USB device by selecting control signal to  oscillator form plural calibration units

To reduce production cost, the present invention provides a microprocessor device for an LCD controller, which includes a memory, a first processing unit, a second processing unit, a first arbiter and a second arbiter. The memory is utilized for storing data. The first processing unit is utilized for executing a first program. The second processing unit is utilized for executing a second program. The first arbiter is coupled to the first processing unit and the second processing unit and utilized for deciding an operation order for the first processing unit and the second processing unit. The second arbiter is coupled to the first processing unit, the second processing unit and the memory and utilized for deciding a memory accessing order for the first processing unit and the second processing unit.

Growing community of inventors

Hsinchu County, Taiwan

Chun-Liang Chen