Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun-Li Chou

Neng-Jye Yang

Wan Hsuan Hsu

Hun-Jan Tao

Shao-Yen Ku

Nai-Chia Chen

Yen-Chiu Kuo

Yu-Li Cheng

Chao-Cheng Chen

Jao Sheng Huang

Chia-Wei Wu

Yu-Yen Hsu

Ya Tzu Chen

Peng-Fu Hsu

Jui-Ping Chuang

Huang-Ming Chen

Pei-Hung Chen

Tsai-Pao Su

Chun-Hung Chao

Syun-Ming Jang Jang

Jyu-Horng Shieh

Chih-Yuan Ting

Yih-Ann Lin

Yi-Chen Huang

Ming-Hong Hsieh

Sheng-Chi Shih

Chi-Yun Tseng

Hobin Chen

Hsin-Ching Shih

Hong-J Tao

An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.

Semiconductor devices and methods of manufacturing

Aspects of the disclosure provide a method. The method includes forming a structure over a substrate, and forming a spacer layer on the structure, wherein the spacer layer has a recess. The method includes forming a mask layer over the spacer layer and in the recess, the mask layer including a first layer, a second layer and a third layer. The method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose the recess of the spacer layer, wherein the opening in the second layer has a first width; and. The method includes removing the second layer using a wet etchant, wherein the opening in the third layer has a second width, and the second with is greater than the first width.

Method and structure of middle layer removal

A middle layer removal method is provided. The method includes providing a substrate having a structure formed on the substrate, and forming a spacer layer on the structure. The method includes forming a mask layer over the spacer layer, the mask layer including a first layer, a second layer over the first layer, and a third layer over the second layer. The method also includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose a bottom surface of the second layer. The method further includes removing the second layer using a wet etchant.

A semiconductor device and method of manufacture comprise placing an etch stop layer of a material such as aluminum oxide over a conductive element, placing a dielectric layer over the etch stop layer, and placing a hardmask of a material such as titanium nitride over the dielectric layer. Openings are formed to the etch stop layer, the hardmask material is selectively removed, and the openings are then the material of the etch stop layer is then selectively removed to extend the openings through the etch stop layer.

Semiconductor device and method

Aspects of the disclosure provide a method. The method includes providing a substrate having a structure formed on the substrate, and forming a spacer layer on the structure. Then, the method includes forming a mask layer over the spacer layer. The mask layer includes a first layer, a second layer over the first layer, and a third layer over the second layer. Further, the method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer with a dry etching process using the third layer as an etch mask to form an opening that exposes a portion of the spacer layer. Then, the method includes removing the second layer using a wet etchant before a formation of a backfill material layer in the opening and over the first layer.

A method of forming a semiconductor device includes forming a conductive feature in a first dielectric layer, forming one or more dielectric layers over the first dielectric layer, and forming a via opening in the one or more dielectric layers, a bottom of the via opening exposing the conductive feature. The method further includes cleaning the via opening using a chemical mixture, and rinsing the via opening using basic-ion doped water after cleaning the via opening.

Chemical clean of semiconductor device

Some embodiments relate to a manufacturing method for a semiconductor device. In this method, a semiconductor workpiece, which includes a metal gate electrode thereon, is provided. An opening is formed in the semiconductor workpiece to expose a surface of the metal gate. Formation of the opening leaves a polymeric residue on the workpiece. To remove the polymeric residue from the workpiece, a cleaning solution that includes an organic alkali component is used. Other embodiments related to a semiconductor device resulting from the method.

Aqueous cleaning techniques and compositions for use in semiconductor device manufacture

A system and method for etching a substrate is provided. An embodiment comprises utilizing an inert carrier gas in order to introduce a liquid etchant to a substrate. The inert carrier gas may prevent undesirable chemical reactions from taking place during the etching process, thereby helping to reduce the number of defects that occur to the substrate and other structures during the etching process.

Semiconductor device and method of manufacture

A wet chemical processing method and apparatus for use in semiconductor manufacturing and in other applications, is provided. The method and apparatus provide for energizing a processing liquid such as a cleaning or etching liquid using ultrasonic, megasonic or other energy waves or by combining the liquid with a pressurized gas to form a pressurized spray, or using both. The energized, pressurized fluid is directed to a substrate surface using a fluid delivery system and overcomes any surface tensions associated with liquids, solids, or air and enables the processing liquid to completely fill any holes such as contact holes, via holes or trenches, formed on the semiconductor substrate.

Method and system for energized and pressurized liquids for cleaning/etching applications in semiconductor manufacturing

Some embodiments relate to methods and apparatus for providing a homogeneous wafer temperature profile in a wafer cleaning tool without introducing unwanted particles onto the wafer. In some embodiments, a disclosed wafer cleaning tool has a processing chamber configured to house a semiconductor wafer. A dispensing arm provides a high temperature cleaning solution to the semiconductor wafer. A heating cup is located within the processing chamber at a position that is around the perimeter of the semiconductor wafer. The heating cup generates heat that increases the temperature of outer edges of the semiconductor wafer by a greater amount than a temperature of a center of the semiconductor wafer, thereby homogenizing an internal temperature profile of the semiconductor wafer.

Apparatus to improve internal wafer temperature profile

Some embodiments relate to a manufacturing method for a semiconductor device. In this method, a semiconductor workpiece, which includes a metal gate electrode thereon, is provided. An opening is formed in the semiconductor workpiece to expose a surface of the metal gate. Formation of the opening leaves a polymeric residue on the workpiece. To remove the polymeric residue from the workpiece, a cleaning solution that includes an organic alkali component is used.

Aqueous cleaning techniques and compositions for use in semiconductor device manufacturing

A method for preventing the formation of contaminating polymeric films on the backsides of semiconductor substrates includes providing an oxygen-impregnated focus ring and/or an oxygen-impregnated chuck that releases oxygen during etching operations. The method further provides delivering oxygen gas to the substrate by mixing oxygen in the cooling gas mixture, maintaining the focus ring at a temperature no greater than the substrate temperature during etching and cleaning the substrate using a two step plasma cleaning sequence that includes suspending the substrate above the chuck.

Method for backside polymer reduction in dry-etch process

After trench line pattern openings and via pattern openings are formed in a inter-metal dielectric insulation layer of a semiconductor wafer using trench-first dual damascene process, the wafer is wet cleaned in a single step wet clean process using a novel wet clean solvent composition. The wet clean solvent effectively cleans the dry etch residue from the plasma etching of the dual damascene openings, etches back the TiN hard mask layer along the dual damascene openings and forms a recessed surface at the conductor metal from layer below exposed at the bottom of the via openings of the dual damascene openings.

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Jhubei, Taiwan

Chun-Li Chou