Chunghwa Picture Tubes, Ltd.

Chun-Kuo Yu

Chun-Yuan Hsu

Chih-Jen Shih

Che-Cheng Kuo

Chih-Fan Su

Chien-Ping Ku

A high-reliability gate driving circuit is disclosed for providing a plurality of gate signals to plural gate lines respectively. The gate driving circuit includes a plurality of shift register stages. Each shift register stage includes a pull-up unit, an energy-store unit, a buffer unit, a discharging unit, a first pull-down unit, a second pull-down unit and a control unit. The pull-up unit pulls up a gate signal according to a driving control voltage and a first clock. The buffer unit receives an input signal. The energy-store unit provides the driving control voltage through performing a charging process based on the input signal. The first pull-down unit pulls down the gate signal according to a control signal. The second pull-down unit pulls down the gate signal according to a second clock having a phase opposite to the first clock. The control unit generates the control signal based on the gate signal.

High-reliability gate driving circuit

The present invention provides a display method of an active matrix display. First, image data is provided, and the image data is divided into a first image section and a second image section. Next, a first black frame section and a second black frame section are respectively inserted into the first image section and the second image section to form a first frame and a second frame. Then, the first frame and the second frame are displayed in turn so as to display the image data.

Display method on active matrix display

A shift register apparatus and a method thereof are provided. The technique manner submitted by the present invention utilizes two NMOS transistors for pulling down the voltage level of the scan signals output by the shift registers within the shift register apparatus to the low level gate voltage, wherein one of the NMOS transistors is controlled by a control unit, and the other NMOS transistor is controlled by a clock signal or the inverted clock signal provided to the shift registers. Therefore, shifting amount of the threshold voltage of those NMOS transistors can trend to be flat, and the reliability of those NMOS transistors can be promoted. In addition, since only one control unit is needed to dispose in each shift register so that the layout area of whole shift register apparatus can be reduced, and the panel with narrow frame size also can be achieved by the present invention.

Growing community of inventors

Taoyuan County, Taiwan

Chun-Kuo Yu