Taiwan Semiconductor Manufacturing Comp. Ltd.

Lextar Electronics Corporation

Far Eastone Telecommunications Co., Ltd.

Chun-Kuang Chen

Ru-Gun Liu

Yung-Sung Yen

Tsai-Sheng Gau

Chih-Ming Lai

Chih-Liang Chen

Charles Chew-Yuen Young

Kam-Tou Sio

Jiann-Tyng Tzeng

Wei-Liang Lin

Chin-Hsiang Lin

Li-Jui Chen

Chi-Cheng Hung

Shih-Wei Peng

Fu-Jye Liang

Shau-Lin Shue

Chung-Ju Lee

Po-Chung Cheng

Chia-Tien Wu

Kuei-Shun Chen

Yung-Hsu Wu

Po-Shen Chen

Chih-Tsung Shih

Ta-Ching Yu

Hui-Ying Chen

Feng-Ling Lin

Hung-Wen Cho

Ken-Hsien Hsieh

Hsien-Cheng Wang

Wen-Hao Chen

De-Fang Chen

Chi-Yeh Yu

Burn Jeng Lin

Ming-Chang Wen

Chia-Cheng Chao

Chung-Cheng Wang

Shun-Li Chen

Ching-Yu Chang

Hui-Ting Yang

Yu-Tien Shen

Chin-Yuan Tseng

Ko-Bin Kao

Yuan-Ching Chen

Wei-Cheng Lin

Shih-Ming Chang

Feng-Cheng Hsu

Tzung-Chi Fu

Pin-Dai Sue

Meng-Hung Shen

Jen-Chieh Shih

Tung-Yu Chen

Tien-I Bao

Shinn-Sheng Yu

Wen-Chuan Wang

Cheng-Hsiung Tsai

Hsin-Chieh Yao

Chih-Ming Ke

Chien-Wei Wang

Sheng-Chi Chin

Tsong-Hua Ou

Chi-Lun Lu

Yao-Ching Ku

Burn-Jeng Lin

Yu-Sheng Chang

Chung-Hsing Chang

Kuan-Hsin Lo

Hui-Chun Lee

Kam-tou Sio

Shu-Hui Sung

Tung-Hung Feng

Hsiao-Wei Yeh

Jacky Huang

Chih-An Lin

Horng-Huei Tseng

Yen-Ming Chen

Li-Chun Tien

Shang-Chieh Chien

Huan-Just Lin

Chien-Chih Chen

Chih-Kung Lee

Chi Ming Yang

Chia-Hui Lin

Jaw-Jung Shin

Tsung-Yao Wen

Joy Cheng

Jen-Yang Chung

Jui-Yao Lai

Wen-Jong Wu

Chien-Nan Yeh

Meng-Wei Chen

Siao-Shan Wang

Jhih-Yu Wang

Wen-Hsin Hsiao

Chen-Hau Wu

Ming-Jhih Kuo

Chew-Yuen Young

Jan-Wen You

Ya-Ling Cheng

Herman Chunghwa Rao

Yu-Hsun Chen

A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Method of fabricating semiconductor device with reduced trench distortions

A test wafer is placed inside a baking module and is baked. Via one or more temperature sensors, a cumulative heat amount delivered to the test wafer during the baking is measured. The measured cumulative heat amount is compared with a predefined cumulative heat amount threshold. In response to the comparing indicating that the measured cumulative heat amount is within the predefined cumulative heat amount threshold, it is determined that the baking module is qualified for actual semiconductor fabrication. In response to the comparing indicating that the measured cumulative heat amount is outside of the predefined cumulative heat amount threshold, it is determined that the baking module is not qualified for actual semiconductor fabrication.

Using cumulative heat amount data to qualify hot plate used for post-exposure baking

A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.

Semiconductor device including source/drain contact having height below gate stack

A filter is used for removing metallic contaminants in a solvent used in microcircuit fabrication. The filter includes a filter housing including a filter membrane for filtering solvent including metallic contaminants, and a magnet arranged about the filter housing and configured to generate a magnetic field to attract the metallic contaminants prior to the metallic contaminants entering the filter membrane. The magnet is arranged such that the magnetic field of the magnet is greater in a periphery of the filter housing compared to a central portion of the filter housing.

Device for applying magnetic field to a filter for reducing metallic contaminants

Using cumulative heat amount data to qualify hot plate used for postexposure baking

Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.

Method for improved critical dimension uniformity in a semiconductor device fabrication process

A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

A layout modification method for fabricating a semiconductor device is provided. The layout modification method includes calculating uniformity of critical dimensions of first and second portions in a patterned layer by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the first and second portions equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. The layout modification method further includes compensating non-uniformity of the first and second portions of the patterned layer according to the uniformity of critical dimensions to generate a modified layout. The first portion is divided into a plurality of first sub-portions. The second portion is divided into a plurality of second sub-portions. Each second sub-portion is surrounded by two of the first sub-portions.

Layout modification method for exposure manufacturing process

A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

A method for collecting information in image-error compensation is provided. The method includes providing a reticle having a first image structure and a second image structure; moving a light shading member to control a first exposure field; projecting a light over the first exposure field; recording an image of the first image structure after the light is projected; moving the light shading member to control a second exposure field; projecting the light over the second exposure field; and recording an image of the second image structure after the light is projected.

Method and apparatus for collecting information used in image-error compensation

Growing community of inventors

Hsinchu County, Taiwan

Chun-Kuang Chen