Industrial Technology Research Institute

Chun-Kai Huang

Wei-Kuo Chia

Ruen-rone Lee

Yu-Ming Lin

Chun-Chieh Hsiao

Tzong-Ming Wu

Kuan-Chou Chen

Muh-Wang Liang

Ping-Yu Hu

Wei K Chia

Chun-Yang Cheng

Shu-Wei Wang

Jiann-Cherng Chen

Sy-Shann Luo

Jiun-Ming Chu

Jan-Han Hsiao

The present invention proposes an apparatus for loading and unloading wafers to and from the semiconductor fabrication equipment. The present invention uses two U-shaped port plate supporters of high rigidity to respectively join with drive devices such as lead screws, shaft bearings, and a lead device, and then join with components such as a port plate, a port door, and a base. The assembly is driven by a motor via timing pulleys, timing belts, idle wheels, a pair of lead screws, shaft bearings, and a lead device. An encoder is matched for feedback control. Thereby, accurate positioning of the main mechanism of the wafer pod responsible for upward and downward movement can be achieved so as to increase the accuracy and reliability of positioning transfer of wafers. Secondarily, the contamination of particles resulted from the motion of the main mechanism can be reduced by using an intake filtering system. Because the present invention adopts a modular design, the drive source of each unit is isolated and the circuit of each unit is hidden so that the whole structure is most compact and the assembling/disassembling and maintenance are easier.

Apparatus for loading/unloading wafers to and from semiconductor fabrication equipment

Methods and systems for storing texels in memory banks in a manner that allows the retrieval of four neighboring texels within a single cycle are disclosed. The four neighboring texels are stored in separate memory banks according to a predetermined set of combinations of 2-D (u, v) coordinate pairs. In interpolating the color value of a color texel C(u, v), a texel buffer retrieves the four neighboring texels in a single cycle to reduce the memory access time. In one embodiment, a plurality of memory banks in the texel buffer are designed in an interleave mode. In an alternative embodiment, a plurality of memory banks in the texel buffer are implemented in a noninterleave mode. In both embodiments, a texel buffer retrieves the four neighboring texels of a color texel C(u, v) within a single cycle according to a predetermined set of criteria.

Methods and systems for storing texels retrievable in a single cycle

A linear address organization for physically storing mip maps and rip maps in memory is disclosed. The subsampled data arrays of the mip maps and rip maps are sequentially stored in continuous subsequences of a continuous sequence of memory addresses. The subsequences of addresses are assigned in order of level of subsampling of the data arrays which make up the mip map or rip map. In the case of a mip map, the subsequences are assigned to the data arrays in order of increasing level of subsampling. In the case of rip maps, the data arrays are segregated into groups according to a first one of the two subsampling directions, such that each array in a particular group has the same level of subsampling in the first direction. Subsequences are assigned to each group of data arrays. The addresses of the subsequences are assigned within each group on a span by span basis where a span includes the texture data in a particular direction of each data array in order of increasing level in the second one of the two subsampling directions. Address generators are also disclosed for assisting in generating linear addresses to texture data with specific coordinates (u,v) in arrays having particular levels of subsampling.

Mip map/rip map texture linear addressing memory organization and

An apparatus and method for blending pixels of a source object and a destination plane of view of 3-D space. The source object overlaps the destination plane of view. Furthermore, the 3-D space may contain an atmospheric light diffusion, i.e., fog or smoke, which produces a 'fog effect.' The apparatus includes multiplexer circuitry which receives first, second, third, fourth and fifth control signals. The multiplexer circuitry also receives a fog blend factor, a source alpha, a destination alpha, a source color, a destination color, a fog color and one. In response to the control signals, the multiplexer circuitry selects three outputs. In particular, in response to the first, second and third control signals, the multiplexer selects as the first output, either: the destination alpha, the source alpha, the fog blend factor, one, the destination color, or one minus one of the aforementioned choices. In response to the first, fourth and fifth control signals, the multiplexer circuitry selects as the second output either: the destination alpha, the source alpha, the fog blend factor, one, the source color, or one minus one of the aforementioned choices. In response to the first control signal, the multiplexer circuitry selects as the third output the destination color or the fog color. The apparatus also includes calculation circuitry which produces a first product, of the source color and the first output of the multiplexer circuitry, produces a second product of the second and third outputs of the multiplexer circuitry, and thereafter adds the two products together.

Apparatus for blending pixels of a source object and destination plane

A method and system are provided for drawing one or more surfaces. The system includes a drawing processor, a frame buffer with z buffer and a display device, such as a display monitor. The drawing processor can perform all of the following steps. A first pixel in a first row is selected. The first pixel is near a first point at which a projection onto a plane of view of a first edge of a first surface intersects the first row of pixels in the plane of view. A first distance from the first point to a second point on the first surface is determined. The first point is a projection onto the plane of view of the second point. The first distance is then corrected by a first value representing a difference in distance between the first distance and a distance from the first pixel to a third point on the first surface. The first pixel overlies, e.g., and is centered at, a point that is a projection onto the plane of view of the third point. The corrected first distance is assigned to the first pixel as representing a distance from the first pixel to the first surface.

Three dimensional graphics system and method with correction to z buffer

A process and apparatus are disclosed for obtaining a texture color value C.sub.r for an object surface point from two texture color values C.sub.ri and C.sub.rj (which themselves may be interpolated texture color values), of texture data points C.sub.i and C.sub.j, respectively. The object surface point is a distance W from the texture data point C.sub.i and a distance 1-W from the object surface point C.sub.j, where W is an n-bit value. The process includes the steps of multiplying each of the texture colors C.sub.ri and C.sub.rj by each integer from 0 to 2.sup.n-1 to produce 2.sup.n -1 products for each color. The product of C.sub.ri with 2.sup.n-1 -W' and the product of C.sub.rj with W' are selected from these produced products, where W' is the rounded product of W and 2.sup.n-1. The two selected products are added together to produce the sum (2.sup.n-1 -W').multidot.C.sub.ri +W'.multidot.C.sub.rj, and the sum thus produced is divided by 2.sup.n-1 to produce the interpolated color. The apparatus for producing the interpolated color uses integer arithmetic for producing the texture color and can operate in a pipelined fashion.

Texture filter apparatus for computer graphics system

A pixel block transfer system has a shifter, at least two registers, an extractor and a mask. Parameter evaluation logic is used to generate most of the parameters needed in the pixel block transfer. The start address of the source block, the start address of the destination block, the number of pixels in the source block and the number of rows in the source block are input to the parameter evaluation logic. The parameter evaluation logic then determines the left shift number, the number of read data, the number of write data, the two write flag, the two read flag, the left mask number and the right mask number. The start addresses, the flags and the read and write numbers are sent to a state machine. These are used to control the pixel block transfer. The left shift number is sent to the shifter and the extractor. It signifies the number of pixels to be shifted left. The left and right mask numbers are sent to the mask to control which pixels are masked and, therefore, not modifiable. The state machine also sends left and right enable signals to the mask.

Word boundary parameter evaluation for bit block transfer operation in a

A display memory architecture which efficiently stores and processes true color and index mode pixels is disclosed. The R, G and B components of true color mode pixels occupy different groups of bit planes in different banks of a frame memory. In addition, consecutive index mode pixels are located in not necessarily consecutive different groups of bit planes in consecutive banks so that a plurality of index mode pixels can be accessed simultaneously in reading and writing operations. Pixel swap circuits are used to swap the order of the R, G and B components of true color pixels and the order of simultaneously accessed index mode pixels, when the order of the accessed locations is different from the order in which R, G and B components of true color pixels or a plurality of index mode pixels are processed by a graphics processor.

Growing community of inventors

Taichung, Taiwan

Chun-Kai Huang