Movellus Circuits Inc.

Chun-Ju Chou

Jeffrey Alan Fredenburg

Yuxiang Mu

A phase detection circuit includes a first phase detection path having a first input to receive a first signal, and a second input to receive a second signal. Asynchronous transition detection circuitry detects an early/late relationship between the first signal and the second signal when at least one of the first signal and the second signal transitions from a first state to a second state. Output circuitry generates a control signal with a value based on the early/late relationship.

Zero-offset phase detector apparatus and method

A delay circuit includes a delay line including at least a first group of delay elements. The delay line is responsive to a first digital delay code to delay an input signal by a first delay value, and responsive to a change from the first digital delay code to a second digital delay code to delay the input signal by a second delay value. Control circuitry generates the first and second digital delay codes. Glitch monitoring circuitry couples to the control circuitry to conditionally gate the change from the first digital delay code to the second digital delay code based on a prediction of a glitch condition.

Glitch-free digital controlled delay line apparatus and method

A delay balancing circuit includes a phase detection circuit, a controller, and a delay circuit. The phase detection circuit receives a reference clock signal having a first frequency, and a feedback clock signal derived from an output clock signal. Detection circuitry detects a phase relationship between the reference clock signal and the feedback clock signal. The phase detection circuit generates a detection signal based on the detected phase relationship. The controller operates to sample the detection signal and to generate and pass an update signal to a delay line to update a delay based on the sampled value. The delay circuit receives a third clock signal and applies a delay, based on the update signal, to the third clock signal to generate the output clock signal.

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Ann Arbor, MI, United States of America

Chun-Ju Chou