United Microelectronics Corp.

Macronix International Co., Ltd.

Chun-Jen Huang

Yao-Jhan Wang

Te-Chang Hsu

Yu-Tsung Lai

Che-Hsien Lin

Cheng-Yeh Huang

Jiunn-Hsiung Liao

Jyh-Cherng Yau

Cheng-Ming Weng

Miao-Chun Lin

Hsin-Yi Ho

Pei-Yu Chou

Chia-Jung Chen

Chun-Chia Chen

Yu-Chih Su

Chun-Hsiung Hung

Kuo-Chih Lai

Jei-Ming Chen

Tzeng-Huei Shiau

Mei-Ling Chen

Yung Feng Lin

Chang-Ting Chen

Caiyun Wu

Qifang Wang

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.

Method for fabricating a metal gate transistor with a stacked double sidewall spacer structure

A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.

Manufacturing method of semiconductor device including conductive structure

A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.

Fin field effect transistor having crystalline titanium germanosilicide stressor layer

Metal gate transistor with a stacked double sidewall spacer structure

Semiconductor device including conductive structure and manufacturing method thereof

Semiconductor structure and fabrication method thereof

In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.

Charge pump system

A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF/NFplasma.

Damascene interconnection structure and dual damascene process thereof

Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.

Semiconductor manufacturing process

A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the charge-trapping memory cell. Then, after the charge-trapping memory cell is completely erased, the first bit line is electrically connected to the second bit line to make a voltage level of the first bit line equal a voltage level of the second bit line such that the voltage level of the first terminal of the transistor equals the voltage level of the second terminal of the transistor.

Scheme of semiconductor memory and method for operating same

A method of cleaning a wafer after an etching process is provided. A substrate having an etching stop layer, a dielectric layer, a patterned metal hard mask sequentially formed thereon is provided. Using the patterned metal hard mask, an opening is defined in the dielectric layer. The opening exposes a portion of the etching stop layer. A dry etching process is performed in the environment of helium to remove the etching stop layer exposed by the opening. A dry cleaning process is performed on the wafer surface using a mixture of nitrogen and hydrogen as the reactive gases. A wet cleaning process is performed on the wafer surface using a cleaning solution containing a trace amount of hydrofluoric acid.

Method of cleaning wafer after etching process

A non-volatile memory and an operating method thereof. The non-volatile memory includes a memory cell array, a first dummy cell array, an address decoding unit and a synchronous programming circuit. The memory cell array includes a first memory cell, and the first dummy cell array includes a first dummy cell. The first dummy cell is adjacent to a first side of a memory cell array and corresponds to the first memory cell. The address decoding unit receives an address signal for decoding. When the address signal is a relative address of the first dummy cell, the synchronous programming circuit controls the first dummy cell and the first memory cell to be synchronously programmed.

Non-volatile memory and operating method thereof

A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.

Structure of metal interconnect and fabrication method thereof

An embodiment of the present invention involves a method of programming a memory cell. The memory cell is in a first state having a maximum initial threshold voltage. The memory cell is to be programmed to one of a plurality of states having a higher target threshold voltage relative to the maximum initial threshold voltage. There is a cue voltage between the maximum initial threshold voltage and the target threshold voltage. The memory cell has a drain region. The method includes applying a drain voltage to the cell by a programming pulse having a first width, determining whether the cell has reached the cue threshold voltage, and if the cell has reached the cue threshold voltage, changing the programming pulse width from the first pulse width to a second pulse width. The second pulse width is smaller than the first pulse width.

Growing community of inventors

Tainan, Taiwan

Chun-Jen Huang