Ememory Technology Inc.

Chun-Hung Lu

Hsin-Ming Chen

Shih-Chen Wang

Ming-Chou Ho

Ching-Hsiang Hsu

Shih-Jye Shen

Chun-Hung Lin

Shao-Chang Huang

Meng-Yi Wu

Chih-Wei Chen

Wen-Hao Ching

Tsung-Mu Lai

Ching-Yuan Lin

Yen-Tai Lin

Cheng-Da Huang

Chien-Hung Ho

Ming-Shan Lo

Shih-Chan Huang

Chiun-Chi Shen

Hong-Yi Liao

Kuan-Hsun Chen

Chien-Han Wu

Shih-Yun Lin

A random bit cell includes a random bit cell. The random bit cell includes a volatile memory unit, a first non-volatile memory unit, a second non-volatile memory unit, a first select transistor, and a second select transistor. The first non-volatile memory unit is coupled to a first data terminal of the volatile memory unit, and the second non-volatile memory unit is coupled to a second data terminal of the volatile memory unit. The first select transistor has a first terminal coupled to the first data terminal of the volatile memory unit, a second terminal coupled to a first bit line, and a control terminal coupled to a word line. The second select transistor has a first terminal coupled to the second data terminal of the volatile memory unit, a second terminal coupled to a second bit line, and a control terminal coupled to a word line.

Random bit cell with memory units

A method of programming a nonvolatile memory cell is provided according to an embodiment of the invention. The nonvolatile memory cell includes a substrate; and a select transistor, a following gate transistor, and an anti-fuse transistor comprising a first gate oxide layer, disposed on the substrate and coupled in series with each other. The programming method includes applying to said nonvolatile memory cell a variable DC voltage source comprising at least one high voltage part for forming a trapping path within the first gate oxide layer and at least one low voltage part for crystallizing the trapping path into a silicon filament.

Method of programming nonvolatile memory cell

A random code generator includes a differential cell array, a power circuit, a voltage detector, a control circuit and a read/write circuit. The power circuit provides a supply voltage to a node. The differential cell array includes plural differential cells. Each differential cell includes two sub-cells. The two sub-cells have process variations. During the enrollment, one sub-cell is programmed, and the other sub-cell is subjected to a program inhibition. In addition, a random code is generated according to the storage state of the differential cell.

Random code generator with differential cells and associated control method

An OTP memory cell including an antifuse unit and a select transistor is provided. The antifuse unit includes an antifuse layer and an antifuse gate disposed on a substrate in sequence, a modified extension doped region disposed in the substrate below the antifuse layer, and a first doped region and a second doped region disposed in the substrate at two opposite sides of the antifuse gate. The select transistor includes a select gate, a gate dielectric layer, a second doped region, and a third doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The second and the third doped region are respectively disposed in the substrate at two opposite sides of the select gate. The doped region, the antifuse layer and the antifuse gate form a varactor.

Antifuse OTP memory cell with performance improvement, and manufacturing method and operating method of memory

A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.

Method for operating one-time programmable read-only memory

A single-poly non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly non-volatile memory cell includes an ion well, a gate formed on the ion well, a gate dielectric layer between the gate and the ion well, a dielectric stack layer on sidewalls of the gate, a source doping region and a drain doping region. The dielectric stack layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the ion well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.

Method for operating single-poly non-volatile memory device

A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.

Operation method of non-volatile memory

The present invention provides a method for accessing a memory. The memory contains M one-time programmable memory blocks, and each has a first memory sector and a second memory sector. The method includes: selecting a first target memory block and reading the first target memory block. The step of selecting a first target memory block is performed by comparing the second memory sectors of N one-time programmable memory blocks from M one-time programmable memory blocks by following a search rule to select the first target memory block.

Method for accessing memory

A memory unit with sensing current stabilization includes: a memory cell; a reference cell for providing a reference current; a current mirror coupled to the memory cell and the reference cell for generating a differential current according to the reference current and a cell current of the memory cell; and a sense amplifier coupled to the current mirror for generating an output voltage according to the differential current.

Growing community of inventors

Hsinchu, Taiwan

Chun-Hung Lu