Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

Other

Chun-Hung Lee

De-Fang Chen

Huan-Just Lin

Chao-Cheng Chen

Ming-Ching Chang

Ching-Feng Fu

Yu-Chan Yen

Tzu-Yen Hsieh

Chia-Ying Lee

Yih-Ann Lin

Teng-Chun Tsai

Li-Ting Wang

Cheng-Tung Lin

Hui-Cheng Chang

Jr-Jung Lin

Chih-Han Lin

Chih-Hsin Ko

Shiang-Bau Wang

Yu Chao Lin

Chia-Wei Chang

Hsin-Chih Chen

Dai-Lin Wu

Chien-Hao Chen

Jeff J Xu

Ming-Chung Liang

Hong-Ji Lee

Bi-Ming Yen

Chia-Chi Chung

Duen-Huei Hou

Chun-Liang Tai

Shih-Chiang Chen

Hsu-Sheng Yu

Yu-Lung Yang

Chang Ming-Ching

Shiuh-Sheng Yu

Chia-Ta Hsieh

Yung-Cheng Lu

Ryan Chia-Jen Chen

Neng-Kuo Chen

Yuan-Sheng Huang

Hua Feng Chen

Hao-Ming Lien

Ta-Hung Yang

Tze-Chung Lin

Chun-Pei Wu

Wei-Che Hsieh

Shih-Chang Tsai

Hsiu-Hao Tsao

Chung-Shu Wu

Shin-Yi Tsai

Lung-Kai Mao

Yi-Cheng Li

Chan Syun David Yang

Po-Hsueh Li

Hung-Wei Lin

Ming-Cheng Deng

Kuo-Chin Liu

Nan-Tsu Lian

Hsin-Fang Su

Shin-Chang Tsai

J H Wang

Tsu Hao Wang

According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Vertical device having a protrusion source

A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.

Fin Field-Effect Transistor and method of forming the same

A method for shallow trench isolation structures in a semiconductor device and a semiconductor device including the shallow trench isolation structures are disclosed. In an embodiment, the method may include forming a trench in a substrate; depositing a first dielectric liner in the trench; depositing a first shallow trench isolation (STI) material over the first dielectric liner, the first STI material being deposited as a conformal layer; etching the first STI material; depositing a second STI material over the first STI material, the second STI material being deposited as a flowable material; and planarizing the second STI material such that top surfaces of the second STI material are co-planar with top surfaces of the substrate.

Semiconductor device and method

A method of fabricating a semiconductor device is disclosed. The method includes providing a semiconductor substrate. Alternating layers of a first semiconductor layer and a second semiconductor layer are formed. The first semiconductor layer is formed of a first semiconductor material, the second semiconductor layer formed of a second semiconductor material different from the first semiconductor material. The alternating layers of the first semiconductor layer and the second semiconductor layer are patterned to form stacks of the alternating layers and to expose lateral edges of the alternating layers in the stacks. Under etch conditions, the lateral edges of the alternating layers in the stacks are exposed to etchant to selectively etch recesses in the lateral edges of the first semiconductor layer such that a size of the recesses is substantially uniform.

Semiconductor devices and methods of manufacturing thereof

A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.

Method of forming an integrated circuit using a patterned mask layer

Fin field-effect transistor and method of forming the same

Devices are described herein that include an epitaxial layer, a cap layer above the epitaxial layer, a gate layer adjacent to the epitaxial layer on which an etching process is performed, a trench above the cap layer, and a source/drain portion includes the epitaxial layer.

Method of forming MOSFET structure

An embodiment is a method including forming a first fin in a first region of a substrate and a second fin in a second region of the substrate, forming a first isolation region on the substrate, the first isolation region surrounding the first fin and the second fin, forming a first dummy gate over the first fin and a second dummy gate over the second fin, the first dummy gate and the second dummy gate having a same longitudinal axis, replacing the first dummy gate with a first replacement gate and the second dummy gate with a second replacement gate, forming a first recess between the first replacement gate and the second replacement gate, and a filling an insulating material in the first recess to form a second isolation region.

FinFET structures and methods of forming the same

Generally, this disclosure provides examples relating to tuning etch rates of dielectric material. In an embodiment, a dielectric material is conformally deposited in first and second trenches in a substrate. Merged lateral growth fronts of the first dielectric material in the first trench form a seam in the first trench. The dielectric material is treated. The treating causes a species to be on first and second upper surfaces of the dielectric material in the first and second trenches, respectively, to be in the seam, and to diffuse into the respective dielectric material in the first and second trenches. After the treating, the respective dielectric material is etched. A ratio of an etch rate of the dielectric material in the second trench to an etch rate of the dielectric material in the first trench is altered by presence of the species in the dielectric material during the etching.

Surface treatment for etch tuning

A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.

Self-aligned nanowire formation using double patterning

Vertical device having a protrusion structure

Growing community of inventors

Hsinchu, Taiwan

Chun-Hung Lee