Taiwan Semiconductor Manufacturing Comp. Ltd.

Novatek Microelectronics Corp.

Industrial Technology Research Institute

Globalwafers Co., Ltd.

Powerchip Technology Corporation

Other

Macronix International Co., Ltd.

Lite-on It Corporation

Teco Electric & Machinery Co., Ltd.

Via Technologies, Inc.

National Taiwan University

National Yang Ming Chiao Tung University

Getac Technology Corporation

Global Unichip Corporation

Philips & Lite-on Digital Solutions Corporation

Chun-Hung Chen

Chih-Ping Chao

Chih-Hung Hsieh

Jhon-Jhy Liaw

Chung-Long Chang

Hung-Cheng Kuo

Chun-Ching Huang

Jye-Yen Cheng

Kuan-Chi Tsai

Wei-Kung Tsai

Jhon Jhy Liaw

Kuo-Hua Pan

Ta-Chun Lin

Hua-Chou Tseng

Chia-Hsin Tung

Kuang-Cheng Tai

Tien-Shao Chuang

Ming-Da Cheng

Harry-Hak-Lay Chuang

Wen-Ching Hsu

Tsung-Yu Yang

Chun-Jen Liao

Wei Sen Chang

Hong-Seng Shue

Huang-Chien Liang

Chih-Yuan Chang

I-Ching Li

Feng-Lin Chan

Kuo-Yu Cheng

He-Wei Huang

Chien-Lung Chu

Kai-Wen Shao

Keng-Yu Chen

Shuo-Wen Jang

Ta-Chien Chiu

Hsing-Pang Wang

Wei-Han Chiang

Ching-Ho Cheng

Ching-Wen Hsiao

Alex Kalnitsky

Hung-Yi Lin

Ching-Chung Hsu

Yang-Hwei Tsuang

Chien-Chih Ho

Wei-Chun Hua

Yi-Sin Wang

Shao-Yu Chen

Fu-Jen Yang

Li-Feng Chen

Chao-Kai Liu

Chia-Yi Su

Hsiang-Chi Chen

Cheng-Chang Hsu

Hou-Chun Ting

Yi-Rong Ko

Ming-Chao Li

Hsin-Hung Ou

Shin-Puu Jeng

Chi-Feng Huang

Shang-Yun Hou

Bao-Ru Young

Ming Zhu

Chien-Hung Zordius Chen

Harry Hak-Lay Chuang

Lee-Wee Teo

Chia-Lun Tsai

Wei-Lun Shih

Wing-Kai Tang

Ting-Hsuan Hung

Tsen-Wei Chang

Chih-Peng Hsia

Mingsian R Bai

Pao-Kang Niu

Yu-Ying Tang

Yi-Chun Su

Hsueh-Yi Lee

Chieh-Hsiang Chang

Chang-Jung Chiang

Chuan Lee

Fon-Yih Tsuang

Wu-Chen Lin

Po-Wei Chen

Weng-Liang Fang

Soon Kang Huang

Shun-Li Wang

Hsiao Ching-Wen

John Chern

Shuang-Neng Peng

Sheng-Hong Tseng

Chien-Chuan Huang

Yung-Fu Lin

Hau-Tieng Wu

Hung-Chun Chang

Tzu-Chi Liu

Tsun-Tu Wang

Ding-Yuan Chen

Jie-Yu Liao

Hao-Jan Yang

Han-Lin Ku

Sam Hong-Yi Huang

A driver circuit, configured to drive a touch display panel, is provided. The touch display panel includes a sensor. The driver circuit includes a timing control circuit and a touch sensing circuit. The timing control circuit is configured to output a touch driving signal to the sensor. The sensor generates a sensing signal according to the touch driving signal. The touch sensing circuit is coupled to the timing control circuit and is configured to receive the sensing signal. The timing control circuit determines a timing of the touch driving signal according to a noise duration signal to drive the sensor to generate the sensing signal.

Driver circuit

In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.

Method of manufacturing semiconductor devices and a semiconductor device

A touch and display integrated circuit (IC) and a touch and display device are disclosed. The touch and display IC includes a first display driving pad set, a second display driving pad set, first touch pad sets, and second touch pad sets. The first display driving pad set and the second display driving pad set are respectively connected to a first display driver and a second display driver on a touch display device through first leading wires. The first touch pad sets are connected to a touch circuit on the touch display device through second leading wires. The second touch pad sets are connected to the touch circuit through third leading wires. The first touch pad sets and the second touch pad sets are disposed between the first display driving pad set and the second display driving pad set, thereby reducing signal interference.

Touch and display integrated circuit and touch and display device

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region of a first conductivity type. The semiconductor device structure also includes a first fin structure and an adjacent second fin structure formed in and protruding from the first well region. The semiconductor device structure also includes a first isolation structure formed in the first well region between the first fin structure and the second fin structure. A first sidewall surface of the first fin structure faces to a second sidewall surface of the second fin structure. The first sidewall surface and the second sidewall surface each extend along at least two directions from a bottom of the first isolation structure to a top of the first isolation structure.

Isolation with multi-step structure

A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.

Method of fabricating Fin-type field-effect transistor device having substrate with heavy doped and light doped regions

A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a first trench and a second trench in a first semiconductor material. The first trench is deeper than the second trench. The method also includes forming a second semiconductor material in the first trench and the second trench, patterning a first portion of the second semiconductor material in the first trench and a first portion of the first semiconductor material below the first portion of the second semiconductor material into a first fin structure, and patterning a second portion of the second semiconductor material in the second trench and a second portion of the first semiconductor material below the second portion of the second semiconductor material into a second fin structure, and forming an isolation structure surrounding the first fin structure and the second fin structure.

Semiconductor structure and method for forming the same

A voltage regulating circuit includes a low-dropout regulator, configured to provide a driving voltage to drive a loading circuit and receive a first detection voltage from a first feedback terminal; and a reference voltage generating circuit, coupled to the low-dropout regulator, configured to receive a second detection voltage from a second feedback terminal. A voltage difference between the first feedback terminal and the second feedback terminal is clamped according to the first detection voltage and the second detection voltage.

Voltage regulating circuit for keeping voltage headroom

An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper.

Organic interposer including a dual-layer inductor structure and methods of forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and an adjacent second fin structure protruding from the semiconductor substrate and an isolation structure formed in the semiconductor substrate and in direct contact with the first fin structure and the second fin structure. The first fin structure and the second fin structure each include a first portion protruding above a top surface of the isolation structure, a second portion in direct contact with a bottom surface of the first portion, and a third portion extending from a bottom of the second portion. A top width of the third portion is different than a bottom width of the third portion and a bottom width of the second portion.

Fin-type field-effect transistor device having substrate with heavy doped and light doped regions, and method of fabricating the same

A mono-crystalline silicon growth apparatus is provided. The mono-crystalline silicon growth apparatus includes a furnace, a support base disposed in the furnace, a crucible disposed on the support base, and a heating module. The support base and the crucible do not rotate relative to the heating module, and an axial direction is defined to be along a central axis of the crucible. The heating module is disposed at an outer periphery of the support base and includes a first heating unit, a second heating unit, and a third heating unit. The first heating unit, the second heating unit, and the third heating unit are respectively disposed at positions with different heights corresponding to the axial direction.

Mono-crystalline silicon growth apparatus

The disclosure provides a method for driving an OLED touch-and-display device, a driving circuit, and an OLED touch-and-display device. The method includes: generating gate driving signals that are sequentially shifted based on the first clock signal (GCK); sequentially applying the gate driving signals that are sequentially shifted to the plurality of GLs; writing display data in a display driving period for each row of pixels, to the row of pixels, wherein a time length of the display driving period depends on a corresponding gate driving signal and is smaller than the clock cycle; and for a display driving period for each of at least one row of pixels, setting a touch detection period corresponding to the display driving period or corresponding to the display driving period for previous row of pixels at least partially overlapping with the display driving period in time.

Method for driving touch-and-display device, driving circuit, and touch-and-display device

A method of dynamic bias control of a source driver bases on data wing level for power-saving. In order to cover the operating conditions of various loads under normal operations, the output buffer circuit operation is biased. The method utilizes the display gray scale difference between a previous data line and an immediately subsequent data line to determine the bias current to be used for the output buffer. When the difference between the current data line display gray scale and the previous data line display gray scale is not large, the bias current of the output buffer can be reduced. When the difference between the current data line display gray scale and the previous data line display gray scale is large, the bias current of the output buffer is increased and the current of the output buffer is adjusted according to different load conditions to save power.

Dynamic bias control of source driver based on data swing level for power saving

Growing community of inventors

Taipei, Taiwan

Chun-Hung Chen