Au Optronics Corporation

Au Potronics Corp.

Chun-Huan Chang

Yung-Chih Chen

Kuo-Chang Su

Chun-Hsin Liu

Yu-Chung Yang

Wei-Li Lin

Kuo-Hua Hsu

Chien-Hao Fu

Min-Feng Chiang

Che-Wei Tung

Kun-Yueh Lin

Yi-Suei Liao

Ya-Ting Lin

Wan-Jung Chen

Shu-Fang Hou

Ming-Chin Lee

Pai-Hung Hsu

Chun-Kai Chang

A display panel includes a display area, a shift register circuit, a first start signal line, and a second start signal line. The shift register circuit is electrically coupled to the display area through a plurality of signal output lines. The first start signal line and the second start signal line are electrically coupled to the shift register circuit. The first start signal line and the second start signal line are both arranged without crossing the signal output lines.

Display panel and method for manufacturing the same

A shift register circuit includes a first pull-down control circuit, a first pull-down circuit electrically connecting to the first pull-down control circuit, a first inversed pulse signal coupling circuit outputting a first inversed pulse signal, a first pull-up circuit outputting a first gate control signal, and a first main pull-down circuit electrically connecting to the first pull-up circuit. The first pull-up circuit receives a first driving signal and a first pulse signal to output the first gate control signal. The first inversed pulse signal coupling circuit duly outputs the first inversed pulse signal to compensate a surge occurring in the first driving signal.

Shift register circuit

A display panel and its gate driving circuit are provided. The gate driving circuit includes a plurality of shift registers. Each of the shift registers includes a first scan signal generator for generating a first scan signal, a second scan signal generator for generating a second scan signal, a first control unit for generating a first control signal, and a second control unit for generating a second control signal. Here, the first control signal and the second control signal are shared by the first scan signal generator and the second scan signal generator. Based on the above, the abatement of signal intensity of the first scan signal and the second scan signal caused by circuit sharing can be precluded, and a chip area occupied by each of the shift registers can be reduced.

Display panel and gate driving circuit thereof

An exemplary gate driving circuit is adapted for driving a display panel including multiple pixels and includes a first gate driving unit string and a second gate driving unit string. The first gate driving unit string includes multiple cascade-connected first gate driving units and receives a start pulse. The first gate driving units are for generating output pulses to drive the pixels. The second gate driving unit string includes multiple cascade-connected second gate driving units and receives the start pulse. The second gate driving units are for generating output pulses to drive the pixels. The output pulse generated from one of the second gate driving units is provided to one of first gate driving units to determine whether to disable the output pulse of the first gate driving unit which receives the output pulse generated from the second gate driving units.

Display panel and gate driving circuit and driving method for gate driving circuit

A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes an input unit and a pull-up unit. The pull-up unit is utilized for pulling up a gate signal according to a system clock and a driving control voltage. The input unit is employed for outputting the driving control voltage according to a control signal and an input signal. The input unit includes a switch device having a first transistor and a second transistor. The first transistor has a first end for receiving the input signal, a gate end for receiving the control signal, and a second end. The second transistor has a first end electrically connected to the second end of the first transistor, a gate end electrically connected to the first end of the first transistor, and a second end for outputting the driving control voltage.

Shift register circuit using a switch device

A clock signal supplying method for shift registers includes following steps: receiving a clock signal; and transmitting the clock signal to two first stage signal transmission paths simultaneously, the first stage signal transmission paths determined by a first control signal whether to be conducted, and further conducted at different time.

Clock signal supplying method and circuit for shift registers

Switch device and shift register circuit using the same

A display panel including plural wiring sets is provided. Each of the wiring sets includes plural wires extending substantially along a straight direction. Each of the wiring sets has a first part and a second part respectively located at two opposite sides of a sealant. The first part is located between the sealant and an active region of the display panel, and a shortest distance of two adjacent wire segments of the first part is larger than a shortest distance of two adjacent wire segments of the second part. In addition, the shortest distance of two adjacent wire segments of the first part may be limited from about 15 &#x3bc;m to about 35 &#x3bc;m. The configuration of wiring set can reduce crosstalk of electric field between two adjacent wires to prevent light leakage and improve display quality.

Display panel

A display panel having a display region and a sealant region is provided. The display panel includes a first substrate, a second substrate, a sealant and a display medium. The sealant is disposed between the first and second substrates and within the sealant region. The display medium is disposed between the first and second substrates and within the display region. The second substrate includes pixel units and wires electrically connected to the pixel units. The pixel units are disposed within the display region, the wires extend to the sealant region from the display region, and at least a portion of the wires in the sealant region has slots. In particular, each of the slots has a side edge adjacent to the edge of the wire which the slot is disposed therein, and the distances from the side edge to the edge of the wire are not equal.

Display panel and pixel array substrate with connecting wires having through-opening

The present invention relates to a shift register and GOA architecture of the same in a display panel comprising a substrate and a plurality of pixels spatially formed on the substrate defining a number of pixel rows, each pixel row having a height of H. The shift register has the plurality of shift register stages disposed spatially and sequentially on the substrate in such a way that the layout of each shift register stage has a height of (j*H), j being an integer greater than one. Each shift register stages is configured to generate j scanning signals for driving j neighboring pixel rows, respectively.

Shift register and architecture of same on a display panel

A liquid crystal display panel includes a display area, a wiring area, and an external circuit area, wherein the wiring area is between the display area and the external circuit area. The liquid crystal display panel includes many pixel structures, external pads and wiring sets. Each wiring set includes a plurality of upper-layer main wires disposed on one plane and lower-layer main wires disposed on another plane, wherein the two planes are parallel. In addition, each upper-layer main wire corresponds to one lower-layer main wire and the shadow which the upper-layer main wire vertically projects on the surface overlaps a part of the corresponding lower-layer main wire. The light leakage around the display area can be eliminated by proper arrangement of main wiring sets, and therefore the display quality is improved.

Liquid crystal display panel

An array substrate is disclosed. The array substrate comprises a substrate, a gate metal layer, a gate insulation layer, a semiconductor layer, a patterned metal layer, a flat layer, and a pixel electrode. The patterned metal layer is disposed on the surface of the semiconductor layer comprising a source and a drain, and on the surface of the gate insulation layer comprising a storage capacitor line and a data line. The storage capacitor line has an extending portion parallel to a scan line. The pixel electrode overlaps parts of the scan line, parts of the data line, parts of the storage capacitor line, and parts of the extending portion. A method for manufacturing the array substrate is also provided.

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Hsin-Chu, Taiwan

Chun-Huan Chang