Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun Hua Chang

Wen-Chih Chiou

Chen-Hua Douglas Yu

Shang-Yun Hou

Der-Chyang Yeh

Shin-Puu Jeng

Li-Hsien Huang

Tsang-Jiuh Wu

Cheng-Hung Chang

Chia-Lin Yu

Ebin Liao

Hsiang-Yi Wang

Darryl Kuo

Hsien-Pin Hu

Shih-Wen Huang

Sung-Hui Huang

Yuan-Hung Liu

Kuang-Wei Cheng

Chi-Hsi Wu

Tzuan-Horng Liu

Chia-Wei Liu

Wen-Hsin Wei

Chien-Ying Wu

Fang-Ting Kuo

Chung-Yu Lu

Tsung-Yang Hsieh

Chih-Ching Lin

Chun-Che Chen

Ren-Wei Xiao

Jhih-Ming Lin

Wen-Jung Chuang

Sheng Yu Lin

A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness Tat a first end of the opening, and a thickness Tat a second end of the opening, and Ris a ratio of Tto T. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness Tat the first end of the opening, a thickness Tat the second end of the opening, Ris a ratio of Tto T, and Ris greater than R.

Semiconductor component having through-silicon vias

An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.

Semiconductor device and method of manufacture

A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner.

Method of making a semiconductor component having through-silicon vias

Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die to a first side of a component using first electrical connectors. After the attaching, at least one of (i) the first die comprises a first fuse, (ii) the first side of the component comprises a second fuse, (iii) a second side of the component comprises a third fuse, the second side being opposite the first side, or (iv) a combination thereof. The method further comprises after the attaching the first die to the first side of the component, blowing the first fuse, the second fuse, the third fuse, or a combination thereof.

Configurable routing for packaging applications

A method of forming a device includes forming a through via extending into a substrate. The method further includes forming a first insulating layer over the surface of the substrate. The method further includes forming a first metallization layer in the first insulating layer and electrically connected to the through via. The method further includes forming a capacitor over the first metallization layer, wherein the capacitor comprises a first capacitor dielectric layer and a second capacitor dielectric layer. The method further includes depositing a continuous second insulating layer over the first insulating layer. The capacitor is within the second insulating layer. The method further includes depositing a third insulating layer over the second insulating layer. The method further includes forming a second metallization layer in the third insulating layer. A bottom surface of the second metallization layer is below a bottom surface of the third insulating layer.

Method of manufacturing a capacitor

A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner.

Semiconductor component having through-silicon vias and method of manufacture

A method of making a metal insulator metal (MIM) capacitor includes forming a copper bulk layer in a base layer, wherein the copper bulk layer includes a hillock extending from a top surface thereof. The method further includes depositing an etch stop layer over the base layer and the copper bulk layer. The method further includes depositing an oxide-based dielectric layer over the etch stop layer. The method further includes forming a capacitor over the oxide-based dielectric layer. The method further includes forming a contact extending through the oxide-based dielectric layer and the etch stop layer to contact the copper bulk layer, wherein the forming of the contact removes the hillock.

Method of forming semiconductor structures including metal insulator metal capacitor

A metal insulator metal (MIM) capacitor includes a base layer and a copper bulk layer in the base layer. The MIM capacitor further includes an etch stop layer over the base layer and the copper bulk layer and an oxide-based dielectric layer over the etch stop layer. The MIM capacitor further includes a capacitor bottom layer over the oxide-based dielectric layer, an insulator layer over the capacitor bottom layer, and a capacitor top layer over the insulator layer.

Semiconductor structures including metal insulator metal capacitor

A method of forming a device comprises forming a through via extending from a surface of a substrate into the substrate. The method also comprises forming a first insulating layer over the surface of the substrate. The method further comprises forming a first metallization layer in the first insulating layer, the first metallization layer electrically connecting the through via. The method additionally comprises forming a capacitor over the first metallization layer. The capacitor comprises a first capacitor dielectric layer over the first metallization layer and a second capacitor dielectric layer over the first capacitor dielectric layer. The method also comprises forming a second metallization layer over and electrically connecting the capacitor.

A method of forming a semiconductor structure includes forming a through-substrate-via (TSV) structure in a substrate. The method includes forming a first etch stop layer over the TSV structure. The method further includes forming a first dielectric layer in contact with the first etch stop layer. The method still further includes forming a second etch stop layer in contact with the first dielectric layer. The method also includes forming a metal-insulator-metal (MIM) capacitor structure in contact with the second etch stop layer. The method further includes forming a first conductive structure through the first etch stop layer and the first dielectric layer, wherein the first conductive structure is electrically coupled with the TSV structure and the TSV structure is substantially wider than the first conductive structure.

Methods of forming semiconductor structures

A semiconductor structure includes a through-substrate-via (TSV) structure disposed in a substrate. A metal-insulator-metal (MIM) capacitor structure is disposed over the substrate. A dual damascene structure disposed over and electrically coupled with the TSV structure, wherein the dual damascene structure includes a via portion and a trench portion A first dielectric layer is disposed around the via portion of the dual damascene structure. A second dielectric layer disposed around the trench portion of the dual damascene, wherein the second dielectric layer is disposed over the MIM capacitor structure.

Semiconductor structures having a metal-insulator-metal capacitor structure

Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. A through via is formed in the interposer, and a capacitor is formed between a lower level metallization layer and a higher level metallization layer. The capacitor may be, for example, a planar capacitor with dual capacitor dielectric layers.

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Zhubei, Taiwan

Chun Hua Chang