Macronix International Co., Ltd.

Macronix Internationalco., Ltd.

Chun-Hsiung Hung

Kuen-Long Chang

Han-Sung Chen

Chung-Kuang Chen

Ken-Hui Chen

Chin-Hung Chang

Wen-Chiao Ho

Nai-Ping Kuo

Shuo-Nan Hung

Su-Chueh Lo

Ray-Lin Wan

Hsin-Yi Ho

Chuan-Ying Yu

Chun-Yi Lee

Shang-Chi Yang

Yi-Te Shih

Ho-Chun Liou

Shih-Chang Huang

Hang-Ting Lue

Chi Lo

Chia-He Liu

Tien-Yen Wang

Yu-Lan Kuo

Yung-Feng Lin

Shin-Jang Shen

Yu-Chen Wang

Yin-Shang Liu

Wen-Yi Hsieh

Chia-Jung Chen

Tzeng-Huei Shiau

Chia-Feng Cheng

Tseng-Yi Liu

Yao-Wu Cheng

Weitong Chuang

Ching-Chung Lin

Kuo-Yu Liao

Yu-Meng Chaung

Ming-Chih Hsieh

Yi-Fan Chang

I-Long Lee

Chih-Ting Hu

Yun-Chen Chou

Tien-Ler Lin

Tom D Yiu

Ji-Yu Hung

Chang-Ting Chen

Chung Kuang Chen

Wen-Pin Tsai

Cheng Ming Yih

Lung-Yi Kuo

Shih-Hung Chen

Meng-Fan Chang

Teng-Hao Yeh

Yi-Ching Liu

Teruhiko Kamei

Chun-Lien Su

Yu-Shen Lin

Yih-Shan Yang

Ful-Long Ni

Chi-Ling Chu

Han Sung Chen

Chia-Ching Li

Wu-Chin Peng

Kong-Mou Liou

Yu Shen Lin

Shou Wei Huang

Fu-Nian Liang

Bo-Chang Wu

Tzung-Shen Chen

Shih-Lin Huang

Jeng-Kuan Lin

Tien-Shin Ho

Chao-I Wu

Ming-Hsiu Lee

Tzu-Hsuan Hsu

Hsiang-Pang Li

Jun Takahashi

Fuchia Shone

Ken Hui Chen

Yung-Chun Li

Chih-Chang Hsieh

Chun-Jen Huang

Chia-Hsing Chen

Ray L Wan

Yung Feng Lin

Cheng-Jye Liu

Kuen Long Chang

Ju-An Chiang

Hsien-Hung Wu

Chien-Hsin Liu

Ti Wen Chen

Fu-Chia Shone

Hsien-Wen Hsu

Hsin Yi Ho

Yu-Ming Hsu

Ting-Chung Hu

Ming-Chao Lin

Hsin-Chien Chen

Kuo Yu Liao

Yuan-Chang Liu

A circuit is provided. The circuit can include sensing circuits configured to sense differences between first and second currents on selected bit lines of an array of memory cells and produce outputs for the bit lines as a function of the difference, and a global programmable non-regular counter configured to continuously provide a count value to each of the sensing circuits in dependence on a clock signal, wherein each sensing circuit, of the sensing circuits, includes (i) a local detector circuit configured to detect a voltage (Vc) generated according to the difference and (ii) a reference voltage selector configured to receive reference voltages from a source and to select a single reference voltage (Vref), and wherein each sensing circuit produces an output according to (i) a difference between Vc and Vref and (ii) a stored count value received from the counter.

Memory sensing with global non-regular counter and/or global multiple reference voltages

Systems, methods, circuits, and apparatus for managing multi-block operations in memory devices are provided. In one aspect, a memory device includes a memory cell array including at least two blocks, a bit line coupled to a string of memory cells in each of the at least two blocks respectively, a common source line (CSL) coupled to strings coupled to the bit line in the at least two blocks, and a circuitry configured to perform a multi-block operation in the memory cell array by at least one of: forming a first current path from the bit line through the strings to the CSL coupled to a ground to discharge a capacitor associated with the bit line that is pre-charged, or forming a second current path from the CSL coupled to a supply voltage through the strings to the bit line to charge the capacitor that is pre-discharged.

Managing multi-block operations in memory devices

A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

Unchangeable physical unclonable function in non-volatile memory

A memory device for artificial intelligence calculation includes a memory structure, a controller chip, and a processer chip. The memory structure includes a first memory chip, and a stack of second memory chips, in which a memory density of each of the second memory chips is greater than a memory density of the first memory chip. The controller chip is electrically connected to the first memory chip and the second memory chips. The processer chip is electrically connected to the controller chip.

Memory device

A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.

Memory device for computing in-memory

Systems, devices, methods, and circuits for managing reference currents in semiconductor devices. In one aspect, a semiconductor device includes: a memory cell array configured to store data in sets of memory cells and circuitry coupled to the memory cell array. Each set of one or more sets of memory cells in the memory cell array is associated with a respective reference current, and memory cells in sets associated with different reference currents have different threshold voltage distributions. The circuitry is configured to: determine information associated with a reference current for a set of memory cells in the memory cell array based on a memory address corresponding to the set, generate the reference current based on the information associated with the reference current for the set, and sense one or more memory cells in the set based on the reference current.

Managing reference currents in semiconductor devices

A memory device and an associated control method are provided. The memory device includes a non-volatile memory array and a memory control circuit. The non-volatile memory array includes M secured memory zones. The memory control circuit is electrically connected to the non-volatile memory array. The memory control circuit provides a set of mapping information and searches a request key in the set of mapping information. The set of mapping information represents correspondences between N access keys and the M secured memory zones. The memory control circuit acquires at least one of the M secured memory zones if the request key is one of the N access keys, and performs an access command to the at least one of the M secured memory zones. M and N are positive integers.

Memory device and associated control method

A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.

Three dimension memory device capable of improving sensing accuracy in high-speed data sensing operation

A three-dimensional memory structure is provided and including a memory array, including a first and a second sub-arrays, each having a first selection line, plural word lines, and a second selection line; a connection structure, including plural connection areas, and at least one of extension structures of the first selection line, the plural of word lines, and the second selection line is coupled to a corresponding connection area of the plurality of connection areas; a pass gate set, arranged under the connection structure and between the first and the second sub-arrays, the pass gate set including plural pass gates, and, the word lines and the second selection line, and the pass gates are respectively coupled to the corresponding connection areas; and a drive circuit, coupled to the pass gate set, and disposed under the connection structure.

3D memory structure and circuit

Systems, devices, methods, and circuits for managing content addressable memory (CAM) devices. In one aspect, a semiconductor device includes: a memory cell array configured to store data in memory cells, and a circuitry coupled to the memory cell array and configured to execute a search operation in the memory cell array according to a search instruction. The search instruction includes at least one of search data or an option code, and the option code specifies, for the search operation, at least one of a search length or a search depth.

Managing content addressable memory devices

Systems, devices, methods, and circuits for managing secure writes in semiconductor devices. In one aspect, a semiconductor device includes a memory array and logic circuitry coupled to the memory array. The logic circuitry is configured to execute a secure write operation in the memory array in response to receiving encrypted information. The encrypted information includes at least one of information of data to be written, an option code, or multiple addresses in the memory array, the option code specifying a way of writing the data on at least one of the multiple addresses in the memory array.

Managing secure writes in semiconductor devices

A compute in memory device comprises a memory array including a plurality of data lines for parallel access to memory array data, and an input/output interface. Data path circuits between the memory array and the input/output interface include a page buffer, each buffer cell of the page buffer including a plurality of storage elements. A plurality of computation circuits is provided connected to respective buffer cells. The computation circuits execute a function of data in the storage elements of the respective buffer cells and can be configured in parallel to generate a results data page including operation results for the plurality of buffer cells. A data analysis circuit is connected to the data path circuits to execute a function of the results data page to generate an analysis result. A register can be provided to store the analysis result accessible via the input/output interface.

In memory data computation and analysis

A sensing module, a memory device, and a sensing method are provided to perform a read operation so that the un-programmed/programmed state of a memory cell is identified. The sensing module includes a sensing amplifier and a current sink, and both are electrically connected to the memory cell. The sensing amplifier generates a sensing current and identifies the un-programmed/programmed state of the memory cell accordingly. The current sink receives a reference current being equivalent to the summation of the sensing current and a cell current flowing through the memory cell. The reference current is constant, and the sensing current is changed with the cell current. The cell current is generated based on a high read voltage and a low read voltage applied to the memory cell. The sensing current is higher if the memory cell is un-programmed, and the sensing current is lower if the memory cell is programmed.

Sensing module, memory device, and sensing method applied to identify un-programmed/programmed state of non-volatile memory cell

Systems, methods, circuits, and apparatus including computer-readable mediums for testing bonding pads in multi-die packages, e.g., chiplet systems. In one aspect, a chiplet system includes multiple integrated circuit devices electrically connected together. The integrated circuit devices include an integrated circuit device including: an integrated circuit, a plurality of first type bonding pads electrically connected to the integrated circuit and electrically connected to at least one other of the integrated circuit devices, and one or more second type bonding pads electrically isolated from the at least one other of the integrated circuit devices. At least one of the plurality of first type bonding pads is configured to be electrically connected to a corresponding one of the one or more second type bonding pads.

Testing bonding pads for chiplet systems

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Hsinchu, Taiwan

Chun-Hsiung Hung