Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun-Hsing Chen

Mill-Jer Wang

Hao Chen

Ming-Cheng Hsu

Clinton Chih-Chieh Chao

Wen-Feng Liao

Shao-Chun Chiu

Fei-Chieh Yang

Sheng-Hsi Huang

A testing device for testing an integrated circuit package is provided, including a printed circuit board, a testing socket, a conductive fastener, a cover, and a conductive element assembly. The printed circuit board includes a first metal layer formed on the bottom surface thereof. The testing socket is disposed above the printed circuit board. The conductive fastener is configured to secure the testing socket to the printed circuit board, wherein the conductive fastener is electrically connected to the first metal layer and the testing socket. The cover is disposed above the testing socket to form a space for accommodating the integrated circuit package between the cover and the testing socket, wherein the cover makes electrical contact with the integrated circuit package. The conductive element assembly is disposed between and electrically connected to the cover and the testing socket.

Testing device for integrated circuit package

A testing device for testing an integrated circuit package is provided, including a printed circuit board having a first surface, a second surface, and multiple conductive layers between the first and second surfaces. A metal layer is formed on the second surface and is electrically connected to one of the conductive layers that is grounded. A testing socket is disposed over the first surface. A conductive fastener secures the testing socket to the printed circuit board and is electrically connected to the metal layer. A cover is disposed over the testing socket to form a space for accommodating the integrated circuit package between the cover and the testing socket. The cover has a conductive surface in contact with the integrated circuit package. A conductive element assembly is disposed between the cover and the testing socket and is electrically connected to the conductive surface and the conductive fastener.

Testing device and method for integrated circuit package

A method for assembling a probe card for wafer level testing of a plurality of semiconductor devices simultaneously is disclosed. The probe card may include a circuit board including wafer level testing circuitry, a partially flexible silicon substrate, a plurality of test probes disposed at least partially in the substrate for engaging a plurality of corresponding electrical contacts in a wafer under test, and a compressible underfill coupling the substrate to the circuit board. The method includes aligning and assembling the foregoing components, and curing the underfill. The probe card may be used for wafer level burn-in testing. In some embodiments, the probe card may include active test control circuitry embedded in the silicon substrate for conducting wafer level high frequency testing.

Method for assembling a wafer level test probe card

A probe card for wafer level testing of a plurality of semiconductor devices simultaneously. The probe card may include a circuit board including wafer level testing circuitry, a partially flexible silicon substrate, a plurality of test probes disposed at least partially in the substrate for engaging a plurality of corresponding electrical contacts in a wafer under test, and a compressible underfill coupling the substrate to the circuit board. The probe card may be used for wafer level burn-in testing. In some embodiments, the probe card may include active test control circuitry embedded in the silicon substrate for conducting wafer level high frequency testing.

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Chu-Pei, Taiwan

Chun-Hsing Chen