United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Faraday Technology Corporation

United Microelectroncis Corp.

Chun-Hsien Lin

An-Chi Liu

Shih-Hung Tsai

Chien-Ting Lin

Ching-Wen Hung

Po-Kuang Hsieh

Feng-Yi Chang

Yu-Ren Wang

Chan-Lon Yang

Jiunn-Hsiung Liao

Sheng-Yuan Hsueh

Kuo-Hsing Lee

Wen-Tai Chiang

Po-Jui Liao

Shao-Hua Hsu

Tsung-Lung Tsai

Chi-Mao Hsu

Chih-Sen Huang

Po-Jen Chuang

Chao-Ching Hsieh

Shin-Chi Chen

Chia-Ming Kuo

Fu-Jung Chuang

Chia Chang Hsu

Guang-Yaw Hwang

Guan-Wei Huang

Hung-Ling Shih

Yeng-Peng Wang

Yu-Cheng Tung

Fu-Che Lee

Chun-Lung Chen

Yi-Hui Lee

Jia-Rong Wu

Kun-Yuan Liao

Chia-Lin Lu

Chien-Ming Lai

Chia-Wen Liang

Yi-Wen Chen

Hsiao-Pang Chou

Chi-Horn Pai

Tong-Jyun Huang

Ying-Tsung Chen

Hon-Huei Liu

Chih-Chung Chen

Yi-Wei Chen

Chien-Hung Chen

Ssu-I Fu

Chih-Chien Liu

Hui-Lin Wang

Chin-Cheng Chien

Shih-Fang Tzou

Chin-Fu Lin

I-Ming Tseng

Chih-Wei Chen

Rai-Min Huang

Ying-Cheng Liu

Yu-Ru Yang

Chiu-Hsien Yeh

Chen-Hua Tsai

Ming-Te Wei

Jie-Ning Yang

Wen-An Liang

Sheng-Huei Dai

Hung-Yi Wu

Jia-Feng Fang

Chia-Wei Liu

Teng-Chun Tsai

Cheng-Hsien Chou

Chien-Hung Zordius Chen

Chen-Yi Weng

Kun-Hsien Lin

Hsin-Fu Huang

Nien-Ting Ho

Wen-Han Hung

Shih-Chieh Hsu

Shui-Yen Lu

Chih-Hao Yu

Chung-Fu Chang

Zhi-Cheng Lee

Che-Hua Hsu

Pei-Yu Chou

Chien-Liang Lin

Ching-Ling Lin

Chih-Kai Kang

Cheng-Guo Chen

Wei-Hao Huang

Ying-Wei Yen

Chien-Liang Wu

Chen-Hsien Hsu

Shao-Wei Wang

Wei-Jen Wang

Chien-Fu Chen

Kun-Yuan Wu

Tsung-Hung Chang

Yao-Chang Wang

Chi-Sheng Tseng

Shang-Yuan Tsai

Ruei-Yau Chen

Te-Wei Yeh

Jung-Tsung Tseng

The invention provides a layout pattern of a semiconductor cell, which comprises a substrate with a first L-shaped MESA region and a second L-shaped MESA region, wherein the shapes of the first L-shaped MESA region and the second L-shaped MESA region are mutually inverted by 180 degrees, a first high electron mobility transistor (HEMT) and a second high electron mobility transistor are located on the first L-shaped MESA region, and a third high electron mobility transistor and a fourth high electron mobility transistor are located on the second L-shaped MESA region.

Layout pattern of semiconductor cell and forming method thereof

A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.

Rinse process after forming fin-shaped structure

The present disclosure provides, the semiconductor device includes a substrate, a first transistor, a capacitor, and two first plugs. The substrate has a high-voltage region and a capacitor region. The first transistor is disposed in the high-voltage region, and includes a first gate dielectric layer, a first gate electrode, and a first capping layer. The capacitor is disposed in the capacitor region and includes a second gate electrode, a second capping layer, a dielectric layer, and a conductive layer. The two first plugs are disposed on the capacitor, wherein one of the two first plugs penetrates through the second capping layer to directly contact the second gate electrode, and another one of the two first plugs directly contacts the conductive layer.

Semiconductor device and method of fabricating the same

The invention provides a semiconductor structure, which comprises a first standard cell and a second standard cell located on a substrate, wherein an isolation region is included between the first standard cell and the second standard cell, a plurality of fin structures and a plurality of gates form a plurality of transistors, which are respectively located in the first standard cell and the second standard cell, and a plurality of single diffusion breaks (SDBs) located in the first standard cell and the second standard cell. A plurality of first dummy grooves in the first standard cell and the second standard cell, and a plurality of second dummy grooves in the isolation region, wherein some of the second dummy grooves overlap the first dummy grooves.

Semiconductor structure and manufacturing method thereof

A method for fabricating semiconductor device includes the steps of providing a substrate having a first region and a second region, forming a first fin-shaped structure on the first region, removing part of the first fin-shaped structure to form a first trench, forming a dielectric layer in the first trench to form a double diffusion break (DDB) structure, forming a first gate structure and a second gate structure on the DDB structure as a bottom surface of the first gate structure is lower than a top surface of the first fin-shaped structure, and forming a contact plug between the first gate structure and the second gate structure on the DDB structure.

Semiconductor device and method for fabricating the same

A method for fabricating a surface acoustic wave (SAW) device includes the steps of forming a first dielectric layer on a substrate, forming a piezoelectric layer on the first dielectric layer, forming a second dielectric layer on the piezoelectric layer, performing a photo-etching process to remove the second dielectric layer for forming a recess in the second dielectric layer, forming a metal layer in the recess, and then performing a planarizing process to remove the metal layer for forming an electrode in the recess.

Surface acoustic wave device and method for fabricating the same

A method for fabricating a semiconductor device includes the steps of: forming a fin-shaped structure on a substrate, forming a gate material layer on the fin-shaped structure, performing an etching process to pattern the gate material layer for forming a gate structure and a silicon residue, performing an ashing process on the silicon residue, and then performing a cleaning process to transform the silicon residue into a polymer stop layer on a top surface and sidewalls of the fin-shaped structure.

A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.

Nanowire transistor and method for fabricating the same

A method for fabricating a surface acoustic wave (SAW) device includes the steps of forming a buffer layer on a substrate, forming a high velocity layer on the buffer layer, forming a medium velocity layer on the high velocity layer, forming a low velocity layer on the medium velocity layer, forming a piezoelectric layer on the low velocity layer, and forming an electrode on the piezoelectric layer. Preferably, the buffer layer includes silicon oxide, the high velocity layer includes graphene, the medium velocity layer includes silicon oxynitride, and the low velocity layer includes titanium oxide.

A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

Magnetoresistive random access memory with metal oxide layer on top surface and sidewall of MTJ

A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

A semiconductor device includes a substrate having a first region and a second region, a first fin-shaped structure extending along a first direction on the first region, a double diffusion break (DDB) structure extending along a second direction to divide the first fin-shaped structure into a first portion and a second portion, and a first gate structure and a second gate structure extending along the second direction on the DDB structure.

A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.

A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

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Tainan, Taiwan

Chun-Hsien Lin