Omnivision Technologies, Inc.

Chun-Hsiang Chang

Chao-Fang Tsai

Zejian Wang

Yingkan Lin

Jingwei Lai

Zheng Yang

Liping Deng

Min Qu

Zhe Gao

Yu-Shen Yang

Lihang Fan

A differential subrange analog-to-digital converter (ADC) converts differential analog image signals received from sample and hold circuits to a digital signal through an ADC comparator. The comparator of the differential subrange ADC is shared by a successive approximation register (SAR) ADC coupled to provide both M upper output bits (UOB) and a ramp ADC coupled to provide N lower output bits (LOB). Digital-to-analog converters (DACs) of the differential subrange SAR ADC comprises 2M buffered bit capacitor fingers connected to the comparator. Each buffered bit capacitor finger comprises a bit capacitor, a bit buffer, and a bit switch controlled by the UOB. Both DACs are initialized to preset values and finalized based on the values of the least significant bit of the UOB. The subsequent ramp ADC operation will be ensured to have its first ramp signal ramps in a monotonic direction and its second ramp signal ramp in an opposite direction.

Differential subrange ADC for image sensor

An arithmetic logic unit (ALU) includes a front end latch stage coupled to latch Gray code (GC) outputs of a GC generator in response to a comparator output. A signal latch stage is coupled to latch outputs of the front end latch stage. A GC to binary stage is coupled to generate a binary representation of the GC outputs latched in the signal latch stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage.

Arithmetic logic unit design in column analog to digital converter with shared gray code generator for correlated multiple samplings

A data transmission circuit of an image sensor. In one embodiment, the data transmission circuit includes a plurality of banks coupled in a series. A peripheral bank of the plurality of transmission banks is coupled to a function logic. Each bank includes a plurality of local buffers coupled to a local buffer control and a plurality of global buffers coupled to a global buffer control. The local buffers are settable to their enabled or disabled state by a bank enable command at the local buffer control. The enabled local buffers are configured to transfer local data to shift registers of their respective bank. The disabled local buffers are configured not to transfer the local data to the shift register of their respective bank.

Data readout power saving techniques for shift register structure

Apparatuses and methods for data transmission in an image sensor are disclosed herein. An example data transmission circuit may include a plurality of transmission banks coupled in series with a first one of the plurality of transmission banks coupled to function logic, where each of the plurality of transmission banks are coupled to provide image data to a subsequent transmission bank in a direction toward the function logic in response to a clock signal, a plurality of delays coupled in series, wherein each of the plurality of delays is associated with and coupled to a respective transmission bank of the plurality of transmission banks, and wherein the clock signal is received by each of the plurality of transmission banks after being delayed by a respective number of delays of the plurality of delays in relation to the function logic.

Image data readout circuit with shared data bus

Counters with various widths for an image sensor. An image sensor includes a plurality of image pixels arranged in rows and columns of a pixel array. A plurality of memory cells are individually coupled to corresponding columns of the pixel array. The memory cells are arranged in a memory bank. The memory bank includes a first memory cell coupled to a first column of the pixel array. The first memory cell includes a first counter having a first width. A second memory cell is coupled to a second column of the pixel array. The second memory cell comprises a second counter having a second width. The first width and the second width are different.

Counter design with various widths for image sensor

A readout circuit includes a comparator coupled to receive a ramp signal an output of a dual conversion gain pixel. A single counter is coupled to the output of the comparator. The counter is coupled to write to only one of a first or a second memory circuits at a time. A first multiplexor is coupled to load either an initial value or an initial memory value from the first memory circuit into the counter. A second multiplexor is coupled to load either a low conversion gain memory value from the first memory circuit or a high conversion gain memory value from the second memory circuit into a single data transmitter, which is coupled to transmit the received memory value to a digital processor.

Dual conversion gain high dynamic range image sensor readout circuit memory storage structure

An example current generator may include a low dropout regulator (LDO) coupled to receive a reference voltage and provide a reference current in response, where the LDO adjusts a current level of the current reference in response to a calibration signal. A current controlled oscillator coupled to receive a reference current copy from the LDO and generate an oscillating signal in response, where a period of the oscillating signal is based at least in part on a level of the reference current copy. A pulse generator coupled to provide an adjustable pulse signal. A counter coupled to determine a number of periods of the oscillating signal occurring during a duration of the pulse signal, and provide a control signal indicative of such, and a digital calibration circuit coupled to receive the control signal and provide the calibration signal to the LDO in response.

Growing community of inventors

San Jose, CA, United States of America

Chun-Hsiang Chang