Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

TSMC Solar Ltd.

Chun-Heng Chen

Chi On Chui

Shu-Han Chen

Ming-Ho Lin

Xiong-Fei Yu

Cheng-I Lin

Yi-Shao Li

Yung-Cheng Lu

Tsung-Ju Chen

Wan-Yi Kao

Che-Hao Chang

Hui-Cheng Chang

Hongfa Luan

Ming-Feng Hsieh

Szu-Ping Lee

Chi-Ming Liao

Sheng-Po Wu

Chi-On Chui

Chia-Wei Hsu

Lee-May Huang

Hong-Fa Luan

Yu-Ru Lin

Liang-Yin Chen

Chen-Ming Huang

Jiun-Ming Kuo

Chih-Chung Chang

Chih-Jen Wu

An-Chun Tu

Chih-Hong Hwang

Chien-Yao Huang

Yi Hsien Lu

Yung-Sheng Chiu

Chen-Hsun Du

Tzu-Huan Cheng

Yu-Hung Chen

Chen-Hsuan Liao

Wen-Chung Liang

Chorng-Jye Huang

Chao-Cheng Lin

Chun-Ming Yeh

Cheng-Yu Peng

Jun-Chin Liu

Chen-Cheng Lin

Wayne Liu

Chen-Chien Li

Kuei-Shu Chang-Liao

Jui-Chung Hsiao

In an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.

Methods of forming semiconductor devices

A device includes a first channel layer, a second channel layer, a gate structure, a source/drain epitaxial structure, and a source/drain contact. The first channel layer and the second channel layer are arranged above the first channel layer in a spaced apart manner over a substrate. The gate structure surrounds the first and second channel layers. The source/drain epitaxial structure is connected to the first and second channel layers. The source/drain contact is connected to the source/drain epitaxial structure. The second channel layer is closer to the source/drain contact than the first channel layer is to the source/drain contact, and the first channel layer is thicker than the second channel layer.

Semiconductor device comprising channel layers with different thicknesses

A method of forming a semiconductor device includes forming a first layer on a semiconductor fin; forming a mask on the first layer, the mask being thicker on a top of the semiconductor fin than along a sidewall of the semiconductor fin. The first layer is thinned along the sidewall of the semiconductor fin using the mask. A second layer is formed on the semiconductor fin, the second layer covering the mask and the first layer. A dummy gate layer is formed on the semiconductor fin and patterned to expose a top surface of the semiconductor fin.

Dielectric layer on semiconductor device and method of forming the same

A method includes forming a dummy gate oxide on a wafer, and the dummy gate oxide is formed on a sidewall and a top surface of a protruding semiconductor fin in the wafer. The formation of the dummy gate oxide may include a Plasma Enhanced Chemical Vapor Deposition (PECVD) process in a deposition chamber, and the PECVD process includes applying a Radio Frequency (RF) power to a conductive plate below the wafer. The method further includes forming a dummy gate electrode over the dummy gate oxide, removing the dummy gate electrode and the dummy gate oxide to form a trench between opposing gate spacers, and forming a replacement gate in the trench.

Non-conformal gate oxide formation on FinFET

A method of forming a nanostructure field-effect transistor (nano-FET) device includes: forming a fin structure that includes a fin and alternating layers of a first semiconductor material and a second semiconductor material overlying the fin; forming a dummy gate structure over the fin structure; forming source/drain regions over the fin structure on opposing sides of the dummy gate structure; removing the dummy gate structure to expose the first and second semiconductor materials under the dummy gate structure; selectively removing the exposed first semiconductor material, where after the selectively removing, the exposed second semiconductor material remains to form nanostructures, where different surfaces of the nanostructures have different atomic densities of the second semiconductor material; forming a gate dielectric layer around the nanostructures, thicknesses of the gate dielectric layer on the different surfaces of the nanostructures being formed substantially the same; and forming a gate electrode around the gate dielectric layer.

NanoStructure field-effect transistor device and methods of forming

In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.

Semiconductor devices having funnel-shaped gate structures

A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.

Gate oxide of nanostructure transistor with increased corner thickness

A method includes forming a fin protruding over a substrate; forming a conformal oxide layer over an upper surface and along sidewalls of the fin; performing an anisotropic oxide deposition or an anisotropic plasma treatment to form a non-conformal oxide layer over the upper surface and along the sidewalls of the fin; and forming a gate electrode over the fin, the conformal oxide layer and the non-conformal oxide layer being between the fin and the gate electrode.

Non-conformal oxide liner and manufacturing methods thereof

A method includes forming a protruding structure, and forming a non-conformal film on the protruding structure using an Atomic Layer Deposition (ALD) process. The non-conformal film includes a top portion directly over the protruding structure, and a sidewall portion on a sidewall of the protruding structure. The top portion has a first thickness, and the sidewall portion has a second thickness smaller than the first thickness.

Non-conformal capping layer and method forming same

Semiconductor device and method

Semiconductor devices having gate structures with slanted sidewalls

Semiconductor device and manufacturing method thereof

A semiconductor device includes a semiconductor substrate and a first dielectric layer. The semiconductor substrate includes at least one fin. The first dielectric layer is disposed on the at least one fin. A thickness of the first dielectric layer located on a top surface of the at least one fin is greater than a thickness of the first dielectric layer located on a sidewall of the at least one fin.

Semiconductor device

Growing community of inventors

Hsinchu, Taiwan

Chun-Heng Chen