Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun Hao Liao

Chu Fu Chen

Mingo Liu

Chun-Wei Hsu

Chia-Cheng Pao

Chiou Jun Yean

Victor Chiang Liang

Chin-Lung Chen

Nang Ping Tu

Jun Yean Chiou

Chao-Jen Cheng

Yu Chuan Liang

Po-Ju Chiu

A driver structure for an organic light-emitting diode (OLED) device is provided. The driver structure includes a front-end-of-line (FEOL) layer; a back-end-of-line (BEOL) layer disposed on the FEOL layer; and a customer BEOL layer disposed on the BEOL layer. The BEOL layer includes a customer BEOL electrical checking structure. The customer BEOL electrical checking structure has a plurality of memory cells that include a first memory cell vertically aligned with and corresponds to two adjacent pixel regions. The customer BEOL layer includes six bottom structures corresponding to the two adjacent pixel regions and connected in series to form a first electrical path and a second electrical path each electrically connected to the first memory cell. The first memory cell is configured to detect an anomaly of electrical resistance of the first and second electrical path.

Display defect monitoring structure

A method includes: providing a substrate defining a scribe line region and a device region adjacent to the scribe line region; depositing a first mask layer over the device region and the scribe line region; patterning the first mask layer to define a plurality of first areas in the device region and a plurality of second areas in the scribe line region, wherein the first areas and the second areas are parallel and extending in a first direction from a top-view perspective; performing a first ion implantation to form first well regions in the first areas and second well regions in the second areas; coupling conductive pads to the second well regions; and performing a test on the second well regions through the conductive pads.

Test structure and testing method thereof

The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.

Semiconductor structure and manufacturing method thereof

An assembly includes a wafer having a top wafer surface and a wafer circumference. The assembly further includes a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view; and an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly further includes an adhesive element configured to affix the device arrangement structure in a stationary position relative to the wafer, wherein the adhesive element includes a tape layer having an adhesive surface attached to the top surface of the device arrangement structure and attached to a surface of the wafer.

Device arrangement structure assembly having adhesive tape layer

An assembly includes a wafer having a top wafer surface and a wafer circumference and a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view. The device arrangement structure also includes an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly has an adhesive element that affixes the device arrangement structure in a stationary position relative to the wafer.

Device arrangement structure assembly and test method

A semiconductor device comprises a first layer, a second layer configured to overlap with the first layer at a plurality of positions, a plurality of first layer contacts configured to be selectively activated to test the first layer for a first layer leakage current, and a plurality of second layer contacts configured to be selectively activated to test the second layer for a second layer leakage current. The first layer contacts are arranged on the first layer on a first side and a second side of the plurality of positions at which the second layer overlaps with the first layer. The second layer contacts are arranged on the second layer on a third side and a fourth side of the plurality of positions at which the second layer overlaps with the first layer. A determined first layer leakage current or second layer leakage current is indicative of the presence of a crystal defect in the semiconductor device.

Method and apparatus for high voltage device crystal defect detection

An integrated circuit device includes a lightly doped region such as the base region of a bipolar junction transistor within a semiconductor body. The device further includes a UV barrier layer formed over the lightly doped region. The UV barrier protects the lightly doped region from damage that can occur during high energy plasma etching or UV irradiation to erase EPROM.

UV protection for lightly doped regions

A device includes a first power supply line carrying a first positive power supply voltage, and a second power supply line carrying a second positive power supply voltage lower than the first positive power supply voltage. The device further includes a protection circuit having a MOS transistor. A diode is coupled to the MOS transistor. The source-to-drain path of the MOS transistor and the diode are serially coupled between the first and the second power supply lines. The diode is forward biased by the first and the second positive power supply voltages.

Growing community of inventors

Hsinchu, Taiwan

Chun Hao Liao