Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Chun-Hao Chang

Shao-Yu Chou

Yu-Der Chih

Min-Shin Wu

Yuhsiang Chen

Gu-Huan Li

Hidehiro Fujiwara

Ching-Wei Wu

Fei-Gwo Tsai

Jui-Ping Chuang

Li-Kong Turn

Hsueh-Yi Chung

Shang-Yun Huang

Yu Hsiang Chen

Shawn Chen

Liang-Chuan Chang

Methods for reading a memory are provided. In response to a first address signal, a first signal is obtained according to first data of the memory and a second signal is obtained according to second data of the memory by a decoding circuit. Binary representation of the first signal is complementary to that of the second signal. A first sensing signal is provided according to a reference signal and the first signal and a second sensing signal is provided according to the reference signal and the second signal by a sensing circuit. An output corresponding to the first sensing signal or the second sensing signal is output in response to a control signal, by an output buffer.

Method for reading memory

A memory circuit includes a non-volatile memory cell, a comparator and a detection circuit. The comparator is coupled to the non-volatile memory cell, and configured to generate a first output signal. The comparator including a first input terminal and a first output terminal. The first input terminal is coupled to the non-volatile memory cell by a first node, and configured to receive a first voltage. The first output terminal is configured to output the first output signal. The detection circuit is coupled to the comparator and the non-volatile memory cell. The detection circuit is configured to latch the first output signal and disrupt a current path between at least the non-volatile memory cell and the comparator. The detection circuit includes a first inverter coupled to the first output terminal of the comparator and configured to generate an inverted first output signal.

Memory circuit and method of operating same

A memory circuit includes a sense amplifier coupled to a non-volatile memory cell, and a detection circuit coupled to the sense amplifier and the non-volatile memory cell. The sense amplifier includes a comparator. The comparator includes a first input terminal coupled to the non-volatile memory cell by a first node, and configured to receive a first voltage, a second input terminal configured to receive a second voltage, and a first output terminal configured to output a first output signal. The detection circuit is configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the sense amplifier. The detection circuit includes a first inverter. A first input terminal of the first inverter is configured to receive the first output signal. A first output terminal of the first inverter is configured to generate an inverted first output signal.

Memories are provided. A memory includes a first memory array, a second memory array and a read circuit. The first memory array is configured to store first data. The second memory array is configured to store second data that is complementary to the first data. The read circuit includes a decoding circuit, a sensing circuit and an output buffer. The decoding circuit is configured to provide a first signal according to the first data and a second signal according to the second data in response to an address signal. The sensing circuit is configured to provide a first sensing signal according to a reference signal and the first signal, and a second sensing signal according to the reference signal and the second signal. The output buffer is configured to provide the first sensing signal or the second sensing signal as an output according to a control signal.

Memory with symmetric read current profile

A memory circuit includes a non-volatile memory cell, a sense amplifier coupled to the non-volatile memory cell, and configured to generate a first output signal, and a detection circuit coupled to the sense amplifier and the non-volatile memory cell. The detection circuit is configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the sense amplifier.

An apparatus for in situ steam generation oxidation are provided. The apparatus includes a reactor chamber. The apparatus also includes a radiant source over the chamber. The radiant source includes a plurality of lamps for heating the reactor chamber. The apparatus further includes a lamphead over the radiant source for adjusting the temperature of the radiant source. In addition, the apparatus includes a gas inlet system coupled to the lamphead. The gas inlet system includes a mass flow controller for adjusting the flow rate of cooling gas into the lamphead. The apparatus includes a gas outlet system, on the opposite side of the cooling gas inlet system, coupled to the lamphead. The gas outlet system includes a pressure controller for accelerating the exhaust rate of the cooling gas.

Apparatus and method for in situ steam generation

A method, of detecting an address decoding error of a semiconductor device, includes: decoding an original address, with an address decoder of the semiconductor device, to form a corresponding decoded address; recoding the decoded address, with an encoder of the semiconductor device, to form a recoded address; making a comparison, with a comparator of the semiconductor device, of the recoded address and the original address; and detecting an address decoding error based on the comparison.

Method of detecting address decoding error

Memories are provided. A memory includes a first memory array, a second memory array, and a read circuit. The first memory array is configured to store main data. The second memory array is configured to store complement data that is complementary to the main data. The read circuit includes a first sense amplifier, a second sense amplifier and an output buffer. The first sense amplifier is configured to provide a first sensing signal according to a reference signal and first data of the main data corresponding to a first address signal. The second sense amplifier is configured to provide a second sensing signal according to the reference signal and second data of the complement data corresponding to the first address signal. The output buffer is configured to provide one of the first sensing signal and the second sensing signal as an output according to a control signal.

Memory with symmetric read current profile and read method thereof

Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes an output buffer. The output buffer is configured to simultaneously obtain first data from the first memory array and second data from the second memory array according a first address signal, and selectively provide the first data or the second data as an output according to a control signal. Binary representation of the first data is complementary to that of the second data.

A system for detecting an address decoding error of a semiconductor device, includes: decoding an original address, with an address decoder of the semiconductor device, to form a corresponding decoded address; recoding the decoded address, with an encoder of the semiconductor device, to form a recoded address; making a comparison, with a comparator of the semiconductor device, of the recoded address and the original address; and detecting an address decoding error based on the comparison.

Method of detecting address decoding error and address decoder error detection system

Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes a first decoder coupled to the first memory array, a second decoder coupled to the second memory array, and an output buffer. The first decoder obtains first data from the first memory array according a first address signal. The second decoder obtains second data from the second memory array according the first address signal. The output buffer selectively provides the first data or the second data as an output according to a control signal. The first data is complementary to the second data.

A method for manufacturing an imitation leather banded structure with noctilucence. The method has following steps: (1) providing an object with a surface; (2) coating a primer layer on the surface; (3) coating a shielding layer and a colored layer sequentially on the primer layer via a color printing mode; (4) coating a predetermined pattern on the colored layer; and (5) covering a transparent ink layer, and performing an imitation leather printing via a UV mask.

Method for manufacturing an imitation leather banded structure with noctilucence

Systems and methods are provided for edge bead removal. A laser beam of approximately a wavelength is received. The laser beam is delivered along a predetermined beam path. The laser beam is projected on an edge portion of a wafer for edge bead removal.

Systems and methods for edge bead removal

Systems and methods for controlling a sense amplifier are provided. First and second MOS transistors of a first type are connected in series between a first voltage potential and a node. A gate terminal of the first MOS transistor is coupled to a first data. A gate terminal of the second MOS transistor is coupled to a second data line. A third MOS transistor of a second type is connected between the node and a second voltage potential. The third MOS transistor has a gate terminal coupled to the first data line. A fourth MOS transistor of the second type is connected between the node and the second voltage potential in a parallel arrangement with the third MOS transistor. The fourth MOS transistor has a gate terminal coupled to the second data line. A control signal provided to a sense amplifier is based on a voltage of the node.

Systems and methods for controlling a sense amplifier

The present disclosure relates to a semiconductor structure which includes a first row of diffusion strap having two sections separated by a first distance, a second row of diffusion strap having two sections separated by the first distance, a third row of diffusion strap having two sections separated by the first distance, a fourth row of diffusion strap having two sections separated by the first distance, a first row of conductive strap over the first row of diffusion strap and the second row of diffusion strap, and a second row of conductive strap over the third row of diffusion strap and the fourth row of diffusion strap. The first row of conductive strap has two sections separated by a second distance. The second row of conductive strap has having two sections separated by the second distance, wherein the second distance is greater than the first distance.

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Taichung, Taiwan

Chun-Hao Chang