Marvell International Limited

Agency for Science, Technology and Research

Mediatek Singapore Pte. Ltd.

Oki Techno Center (singapore) Pte Ltd.

Chun Geik Tan

Randy Tsang

Yonghua Song

Uday Dasgupta

Yui Lin

Meng Long

Naratip Wongkomet

Tieng Ying Choke

Dan Ping Li

Chunwei Chang

Masaaki Itoh

Renliang Zheng

A system and method for frequency hopping precalibrates a subset of a plurality of channels, storing the channels' associated curves in a computer readable medium. Before hopping to a new channel, decision making circuitry can access the precalibrated curves. If the destination channel has an associated curve, then the system can use the values from that curve when hopping to a new channel. If the destination channel does not have an associated precalibrated curve, then the system can identify a closely situated channel with a precalibrated curve and use an offset value to settle at the destination channel. According to another aspect of the present invention, the offsets can be updated. According to a further aspect of the invention, the updated can be done dynamically.

Agile frequency synthesizer scheme for fast-hopping, low phase noise applications

A differential ring oscillator includes a plurality of delay stages connected in a ring. At least one of the delay stages includes: a current source, arranged to generate a bias current according to a coarse tuning signal; a latching circuit arranged to generate a differential output signal to a next delay stage according to a differential input signal from a previous delay stage; a capacitive array arranged to provide a first capacitance according to a fine tuning signal; and a varactor device arranged to provide a second capacitance according to a controllable signal for locking an oscillating frequency of the differential ring oscillator to a target frequency. The coarse tuning signal and fine tuning signal are arranged for adjusting the oscillating frequency of the differential ring oscillator to, respectively, reach a predetermined frequency range including the target frequency and to approach the target frequency in the predetermined frequency range.

Differential ring oscillator and method for calibrating the differential ring oscillator

A signal generator includes: an adjusting circuit arranged to adjust a first amplitude of an oscillating signal to generate an adjusted oscillating signal; and a resistor ladder circuit arranged to receive the adjusted oscillating signal to generate a plurality of candidate output oscillating signals having a plurality of different amplitudes respectively and output an output oscillating signal selected from the candidate output oscillating signals.

Signal generator and signal strength detecting circuit having the signal generator installed therein

Agile frequency synthesizer scheme for fast hopping, low phase noise applications

Energy-efficient timing circuits are described. Such circuits may include a biasing circuit configured to provide a control bias current to a voltage-controlled oscillator (VCO). The biasing circuit may repetitively switch between a normal-power operating mode and a reduced-power operating mode. During the normal-power operating mode, the biasing circuit may generate a control voltage representative of a desired control bias current for the VCO. By then storing the control voltage using a device, such as a capacitor, much of the biasing circuit may be turned off during the reduced-power operating mode.

Power-efficient biasing circuit

A mixer includes first and second differential input pairs that include first and second transistors. First and second bias transistors receive a first signal of a differential input signal that is the one of a first phase and a second phase, and that respectively communicate with first terminals of the first and second transistors of the first differential input pair. Third and fourth bias transistors receive a second signal of the differential input signal, and that respectively communicate with first terminals of the first and second transistors of the second differential input pair. First and second capacitive elements have first and second ends that respectively communicate with the first terminals of the first and second transistors of the first and second differential input pairs. Four current sourcing elements respectively communicate with first terminals of the first, second, third, and fourth bias transistors.

Wireless transceiver components with improved IQ matching

A capacitor bank adapted to provide a variable capacitance to an electronic circuit is provided. The capacitor bank has at least a most significant bit and a least significant bit and includes a first capacitor cell having a first capacitance value and disposed between a first node and a second node, thereby forming the most significant bit. The capacitor bank also includes a second capacitor cell having a second capacitance value and disposed between the first node and the second node, thereby forming the least significant bit. The second capacitance value is less than the first capacitance value. Additionally, the second capacitor cell includes a first T-network capacitor unit in electrical communication with a source of a transistor and a second T-network capacitor unit in electrical communication with a drain of the transistor.

T-network capbank

A frequency divider comprises a first differential input pair, a second differential input pair, a first capacitive element having first and second ends, a second capacitive element having first and second ends, and four current sourcing elements. The first differential input pair includes first and second transistors that receive a differential local oscillator signal. The second differential input pair includes first and second transistors that receive the differential local oscillator signal. The first capacitive element communicates with first terminals of the transistors of the first differential input pair. The second capacitive element communicates with first terminals of the transistors of the second differential input pair. The four current sourcing elements respectively communicate with the first terminals of the transistors of the first and second differential input pairs.

An oscillating circuit having improved noise degeneration includes an oscillator and a noise degeneration circuit. The oscillator is adapted to provide a differential oscillating signal between first and second output terminals, and includes first and second transistors in communication with the first and second output terminals. The noise degeneration circuit includes cross-coupled capacitors and cross-coupled third and fourth transistors operated in a linear region. The noise degeneration circuit reduces the low frequency gm of the first and second transistors to lower the effect of flicker noise. At relatively high frequencies, the capacitors provide a virtual AC ground to the source terminals of the first and second transistors. The noise degeneration circuit receives a voltage signal from a biasing circuit adapted to track variations in electrical characteristics of the third and fourth transistors.

Flicker noise degeneration technique for VCO

A Gigabit/s transimpedance amplifier system includes a forward-path amplifier section with a very large bandwidth and an overall frequency-selective feedback section which is active only from DC to low frequencies. The forward-path of the amplifier comprises a regulated cascode for receiving the input signal, a regulated cascode for receiving the feedback signal, a single-ended to differential converter and an output buffer. Stability and frequency selection is achieved by a bandwidth-limited operational amplifier in the feedback path. The Miller multiplication of a capacitive means in the operational amplifier creates a low-frequency pole and stabilizes the feedback loop and thereby limits the frequency range of the feedback.

Multi-gigabit/s transimpedance amplifier for optical networks

A biasing circuit for a CMOS passive mixer core to stabilize its conversion gain, linearity and noise figure. The RF inputs are fed differentially from the two RF ports, the LO inputs are fed differentially from the two LO ports, and the IF outputs are obtained at the two IF ports. The biasing circuit comprises a reference current derived from the bandgap voltage and a n-channel MOSFET transistor. The conversion gain is stabilized by keeping the Vgs&#x2212;Vth value of the passive mixer core almost constant at all process corners, temperature and power supply changes. This is achieved by implementing Vs in such a way that it will increase the same amount as VDD decreases, and that Vs will decrease the same amount as Vth increases.

Threshold voltage (Vth), power supply (VDD), and temperature compensation bias circuit for CMOS passive mixer

This invention provides a circuit and a method for programmable counters. It consists of a circuit and a method for unique programmable counters that provide half-integral as well as integral steps, such as 1.5, 2, 2.5, 3, 3.5, 4. This circuit and method are the first implementations of providing programmable counting with half-integral steps. The circuit and method of this invention can be extended via the cascading of toggle flip flops at the front end of the circuit of this invention. This provides the ability to enhance the speed of normal integral step counting applications. In addition, the cascading of the multiple copies of the circuit of this invention provides the ability to provide other fractional programmable counters. A key advantage of this invention is that the method of this invention is general enough to use any other type of counter sub-component beside the binary counter sub-component of this invention.

Growing community of inventors

Singapore, Singapore

Chun Geik Tan