Intel Corporation

Chun Fung Kitter Man

Zion S Kwok

Scott Nelson

Jennifer K Wong

Bose-Chaudhuri-Hocquenghem (BCH) decoder architectures which execute a plurality of different algorithms to calculate an error location polynomial. The multiple algorithms may be implemented in a storage controller for increased throughput per gate count. Codewords needing up to a threshold number of corrections may be processed via a first algorithm while those with a greater number of corrections may be processed via the second algorithm. In embodiments, the Peterson-Gorenstein-Zierler (PGZ) algorithm and the Berlekamp-Massey algorithm (BMA) are executed either serially or in parallel to increase throughput of the decoder.

BCH decoding with multiple sigma polynomial calculation algorithms

Methods and apparatuses for Bose-Chaudhuri-Hocquenghem (BCH) decoding utilizing Berlekamp-Massey Algorithm (BMA) and Chien Search. The BMA may utilize one or more of a scalable semi-parallel shared multiplier array, a conditional q-ary inversionless BMA and/or a conditional binary Inversionless BMA. The Chien Search may be accomplished utilizing a non-rectangular multiplier array.

Error correction mechanisms for flash memories

Various embodiments of the invention pertain to a technique of recovering data from a portion of a non-volatile memory which was not reliably read because the number of read errors exceeded the ability of the ECC process to correct those errors. For each cell in that portion of memory, a quantized estimate is made of the amount of offset in the read reference voltage that is predicted to correct for any systematic noise that may have affected the reading of that cell. For each quantized offset, the read reference voltage is adjusted by that amount and data from the relevant cells is read. The combined results for all the cells are then processed through the ECC again.

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Chun Fung Kitter Man