Icube Corp.

Shinestar LLC

Chun-Chu Archie Wu

Chun Chiu Wong

Pei Sern

A FAX-through data network includes a receiver side LAN end station and a sender side LAN end station. A first converter receives a FAX communication from the sender FAX and generates a FAX packet. The FAX packet includes a predefined session port number and a receiver FAX-network ID. A FAX-network server receives the FAX packet, extract the receiver FAX-network ID, performs a lookup of a destination IP address in a mapping table and forwards the FAX packet to the destination IP address. A second converter intercepts and identifies the FAX packet, extracts the FAX communication from the FAX packet, establish a communication with the receiver FAX without routing a signal through the PSTN and transmits the FAX communication to the receiver FAX machine. A remote access appliance control apparatus includes an appliance side LAN end station. An appliance control packet is generated by the remote network user and includes a predefined session port number, an appliance network ID and the control command. An appliance network server receives the appliance control packet, extracts the appliance network ID, looks-up a corresponding destination IP address in a mapping table, and forwards the appliance control packet to the destination IP address. An appliance converter intercepts and identifies the appliance control packet, extracts the control command and asserts the control command to the appliance using the appliance communication protocol. Advantages include the ability to share the IP address of a LAN end station. The invention also eliminates local and long distance toll cost charge for FAX communication.

Fax through data network and remote access network appliance control apparatus and method

A dynamically configurable network buffer includes a buffer manager organizing a buffer memory into a set of uniform sized packet buffers, each of which is large enough to store the largest possible data packet that may be transmitted through the network switch. The buffer manager further subdivides each packet buffer into a set of smaller packet cells of uniform size. When an incoming data packet arrives at the network buffer, the buffer manager determines its size. If the packet is too large to be stored in a single packet cell, the buffer manager stores the packet by itself in an unoccupied packet buffer. If the packet is small enough to be stored in a single packet cell, the buffer manager stores the packet in an unoccupied packet cell. The network buffer can increase or decrease packet cell size in response to input configuration data.

Dynamically configurable buffer for a computer network

A buffer monitor includes a first counter for counting bits of incoming data as they arrive at a data buffer that stores and then forwards the incoming data. Each bit of outgoing data resets the first counter's count. If its count reaches a first limit before being reset by an outgoing data bit, the first counter asserts an alarm. The buffer monitor also includes a second counter for counting bits of outgoing data as they depart the buffer. Each bit of incoming data resets the second counter's count. If its count reaches a second limit level before being reset by an incoming data bit, the second counter asserts an alarm. The first counter will sound an alarm when the buffer fails to forward output data after having received a substantial amount of input data. The second counter will assert an alarm when the buffer has forwarded a substantial amount of output data without having received any input data. Neither counter will assert an alarm when the buffer stops forwarding data simply because it hasn't received any data to forward.

Apparatus for detecting data buffer faults

An MxN dynamic spare column replacement memory system for storing M N-bit data words includes a random access memory (RAM) formed by a rectangular array of M rows and N+S columns of single-bit memory cells. Each row has a unique address and stores an N-bit word using a selected set of N of its N+S cells. An N-line parallel data bus provides data access to the DRAM. Responding to a switching instruction from a switch controller at the start of each memory access cycle, a crossbar switch selectively connects each of the N lines of the data bus to a separate one of the N+S columns. Thus during a memory read or write access cycle the N data lines access N cells of an addressed row columns. The remaining S cells of the row are unused. A host computer occasionally checks the DRAM for defective memory cells, and upon finding a defective cell or cells in any row, the host stores the row address and a switching instruction in the switch controller. At the beginning of each memory access cycle, the switch controller compares the DRAM address to its stored list of addresses of rows having a defective cell. If the current DRAM address matches a stored address, the switch controller switches data bus lines from columns containing the defective cell to spare columns in accordance with a switching instruction stored with the address. Thus spare cells are assigned for replacement of defective cells on an address-by-address basis.

Growing community of inventors

San Carlos, CA, United States of America

Chun-Chu Archie Wu