Au Optronics Corporation

Chun-Ching Wei

Yang-En Wu

Wei-Cheng Lin

Shih-Hsun Lo

Lee-Hsun Chang

Kun-Hong Chen

Yu-Wen Lin

Chen-Lun Chiu

Shih Hsun Lo

Hung-Hsiao Lin

Yen-hsien Yeh

Cheng-Liang Ma

A shift register includes a signal generating circuit, a driving circuit, a reset circuit, and a control switch. The signal generating circuit includes a first switch for generating a first output signal according to a clock signal while the first switch is turned on, and a second switch coupled to an output end of the shift register for generating and transmitting a second output signal to the output end of the shift register according to the clock signal while the second switch is turned on. The driving circuit is for controlling the first and second switches according to an input signal received from an input end of the shift register. The reset circuit is for turning off the first and second switches and resetting the output signal outputted by the output end. The control switch is for resetting the output signal outputted by the output end.

Shift register

A shift register includes a signal generating circuit for generating an output signal at an output end of the shift register according to a first clock signal while the signal generating circuit is turned on; a driving circuit, electrically coupled to the signal generating circuit, for generating a driving signal to control the signal generating circuit according to an input signal received from an input end of the shift register; a feedback circuit, electrically coupled to a next stage shift register, for transmitting a control signal while the feedback circuit is turned on by the next stage shift register; and a control switch, electrically coupled to the signal generating circuit and the feedback circuit, for turning off the signal generating circuit while the control switch is turned on by the control signal from the feedback circuit.

Shift register turning off a signal generating circuit according to a signal from a feedback circuit

A liquid crystal display and a shift register unit thereof are provided. The shift register unit includes a first switch, a second switch, and a level shift circuit. The first switch has a first input terminal, a first control terminal, and a first output terminal. The second switch has a second input terminal, a second control terminal, and a second output terminal. The second control terminal is coupled to the first output terminal and the level shift circuit. When the first switch is enabled, the first input terminal receives an input signal converting the voltage of the second control terminal into a first voltage for turning on the second switch. The second output terminal outputs a first clock signal to a scan signal line. When the level shift circuit is enabled, the voltage of the second control terminal is converted into a second voltage for turning off the second switch.

Liquid crystal display and shift register unit thereof

Display panels capable of eliminating reliability issues due to high switching frequency. The display panel comprises a data driver outputting first, second, third and fourth data signals in sequence through a data line, a scan driver outputting first and second scan signals in sequence through first and second scan lines and an auxiliary driver generates first and second auxiliary signals in sequence, and first and second display cells commonly receives the first scan signal through the first scan line and receives the first and the second data signal through the data line, and a first switch is coupled to the data line and the second display cell, turning on and off in sequence according to the first auxiliary signal when the first scan signal is applied thereto such that the second and the first display cells receive the first and the second data signals in sequence.

Display panels

A backup shift register module having at least two backup shift registers is used to repair a defective main shift-register module. A normally open link is provided between the input of first backup shift register and the input of each odd-numbered main shift register, and between the output of first backup shift register and the input of each even-numbered main shift register. A normally open link is provided between the input of second backup shift register and the input of each even-numbered main shift register, and between the output of second backup shift register and the input of each odd-numbered main shift register. If one main shift register is defective, the input and output of the defective shift register are disconnected from the cascade link, and the normally open links are connected to the input of the defective shift register and the output of the next shift register are connected.

Backup shift register module for a gateline driving circuit

A shift register having individual driving nodes is disclosed. The shift register includes a first clock pull-down module, a second clock pull-down module, a key pull-down module, a self feedback module, and a driving output unit. The first clock pull-down module is used to pull-down the potential of a gate line to a low voltage when the first clock signal is in a high voltage level. The second clock signal pull-down module pulls down the potential of the gate line to the low voltage when the second clock signal is in a high voltage level. The key pull-down module rapidly pulls down the potential of the gate line to the low voltage level after the gate line outputs an output signal. The self feedback module is used to output a driving signal to the key pull-down module. The driving signal output unit outputs a next stage driving signal which is irrelative to the operation of the previous stage shift register.

Shift register with individual driving node

A shift register includes a signal generating circuit for generating an output signal at an output end of the shift register in response to a clock signal while the signal generating circuit is turned on, a driving circuit electrically coupled to the signal generating circuit for controlling the signal generating circuit in response to an input signal received from an input end of the shift register, a primary reset circuit electrically coupled to the signal generating circuit for turning off the signal generating circuit and resetting the output signal from the output end, and a feedback circuit electrically coupled to the output end and the major reset circuit for controlling the primary reset circuit in response to the output signal and the clock signal.

A shift register circuit having shift registers comprising a first transistor having a gate and a first source/drain for receiving an output signal of a pre-stage shift register, a second transistor having a gate coupled to a second source/drain of the first transistor, a first source/drain coupled to a first clock signal, and a second source/drain coupled to a output, a first pull-down module coupled to the output terminal, for receiving the first clock signal, wherein the output is coupled to a first voltage level when the output signal of pre-stage shift register and the first clock signal are at low voltage level, and a second pull-down module coupled to the output and a second clock signal, wherein the output is coupled to a first voltage level when the output signal of pre-stage shift register and the second clock signal are at low voltage level.

Shift register circuit

A shift register without a feedback signal of a post-stage shift register utilizing a latch mechanism and a clock signal to control the voltage of an output of the shift register is provided. The shift register reduces the transistor size and the circuit layout area. The shift register also improves the issue the overlapping between two adjacent shift registers to reduce the after-image of a liquid crystal display.

A shift registers circuit having a series of cascading shift registers comprises a first transistor coupling to an output signal of a pre-stage shift register, a second transistor coupling to the first transistor, an output and a first clock signal, and a pull-down module coupling to the output, output signals of pre-stage and post-stage shift register, a second and a third voltage level. When the second transistor turns on and the first clock signal is at high voltage level, the output is at a first voltage level. When the signal of post-stage shift register is at first voltage level, the output is at the third voltage level.

A shift register in an amorphous-silicon gate driver comprises a pull-up transistor and two pull-down modules. The pull-up transistor produces a positive pulse when the clock signal is high and the gate of the pull-up transistor is also high. The gate of the pull-up transistor is pulled down to a negative voltage level Vss by two pull-down transistors in the pull-down modules. Each pull-down module also has a further pull-down transistor to keep the output terminal at Vss after the output pulse is produced. The two pull-down modules are operated in a cooperative manner so that each pull-down transistor is conducting approximately 50% of the time. The gates of the pull-down transistors are kept at a positive voltage level approximately 50% of the time and at Vss' approximately 50% of the time with Vss&#x2032; being more negative than Vss.

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Taipei, Taiwan

Chun-Ching Wei