Vixs Systems, Inc.

Ati International Srl

Ati Technologies Ulc

Chun-Chin David Yeh

Philip L Swan

Eric Young

Indra Laksono

Edward George Callway

Edward Hong

Xin Guo

Yuxin Chen

Wendy Wai Yin Cheung

Allen J C Porter

Qi Yang

Rajat Gupta

A processor is configured to store color component values associated with a first subset of vertices of a three-dimensional (3-D) look up table (LUT) in a first subset of memory elements. The color component values are defined according to a destination gamut. A data select module is configured to access the color component values from the first subset of the memory elements concurrently with the processor storing color component values associated with a second subset of the vertices of the 3-D LUT in a second subset of the memory elements. The data select module is configured to access the color component values from the first and second subsets of the memory elements in response to the processor storing the color component values associated with the second subset of the vertices of the 3-D LUT in the second subset of the memory elements. This process can be extended to additional subsets.

Multiple stage memory loading for a three-dimensional look up table used for gamut mapping

A video device includes a codec engine to process video data to generate a stream of pixel blocks representing a picture of a sequence of pictures represented by the video data, an image processing module to receive the stream of pixel blocks via a local path between the codec engine and the image processing module and to perform at least one image processing function for the picture using pixel blocks of the stream of pixel blocks received via the local path to generate image processing result data representative of the picture. The video device further includes a storage interface coupleable to a storage component, the storage interface to provide the image processing result data for storage at the storage component.

Codec engine with inline image processing

A video processing device includes a video processing unit that decodes a video input signal into a decoded video signal in accordance with a video compression protocol, based on uncompressed video frame data. A tile engine includes a tile accumulation module that accumulates the uncompressed video frame data into a plurality of tile units, wherein each of the plurality of tile units includes a plurality of video span units. A tile compression/decompression module generates compressed video frame data for storage in a compressed video frame buffer by compressing the plurality of video span units into a plurality of compressed video span units and further that retrieves the compressed video frame data from the compressed video frame buffer by retrieving the plurality of compressed video span units and generating the uncompressed video frame data by decompressing the plurality of compressed video span units.

Video processor with reduced memory bandwidth and methods for use therewith

An integrated circuit is interfaced with at least one dynamic random access memory (DRAM) via a memory interface. A plurality of user test options are received. The testing of the memory interface is controlled in accordance with the plurality of user test options. Test data, generated as a result of the testing of the memory interface, is stored.

DRAM memory controller with built-in self test and methods for use therewith

A method and apparatus for independent video and graphics scaling in a video graphics system is accomplished by receiving a video data stream, wherein the video data stream includes video data in a first format. A graphics data stream is also received, and the graphics data stream includes graphics data in a second format. The video data of the video data stream is scaled based on a ratio between the first format and a selected video format to produce a scaled video stream. Similarly, the graphics data of the graphics data stream is scaled based on a ratio between the second format and a selected graphics format in order to produce a scaled graphics stream. The scaled video stream and the scaled graphics stream are then merged to produce a video graphics output stream.

Method and apparatus for independent video and graphics scaling in a video graphics system

A method and apparatus is presented for combining multiple data elements to produce resultant data elements, where the data elements used for combination are reused after being loaded into memory on an integrated circuit. The apparatus includes a memory, where the memory stores a plurality of lines of data. The apparatus further includes a circular line buffer operably coupled to the memory, where the circular line buffer stores a plurality of line elements from a portion of the plurality of lines of data. A read addressing block operably coupled to the circular line buffer generates a number of read pointers corresponding to the circular line buffer. Each of the read pointers is used to address the circular line buffer to retrieve one of the data elements from a different line stored in the circular line buffer. A combination block combines the line elements selected by the read pointers to produce a result element. A write pointer coupled to the circular line buffer is utilized to store data from the memory to the circular line buffer, where data stored in the circular line buffer replaces data which has already been read and used by the combination block. A controller operably coupled to the memory, the combination block, the circular line buffer, the read dressing block, and the write pointer provides control information such that the line element data in the circular buffer is read and replaced in an optimized manner that reduces the amount of memory required to store the line data elements for processing.

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North York, Canada

Chun-Chin David Yeh