Via Technologies, Inc.

Fulian Precision Electronics (tianjin) Co., Ltd.

Chun-Chih Yang

You-Ming Chiu

Yung-Chung Chang

Shu-Tzu Wang

Min-Shu Wang

Chun-You Wang

A method of improving an efficiency of updating rule data stored in a block chain receives a rule updating request and obtains data as to the existing rule (rule data) in response to the rule updating request. Each obtained rule data is analyzed for compliance with a predefined rule strategy. When the obtained rule data is determined as complying, a priority level of each obtained rule data is confirmed. The obtained rule data is authenticated based on the priority level and a block chain authentication mechanism. When the obtained rule data is authenticated, the rule data stored in each block chain node in the block chain is updated. An electronic device and a computer readable storage medium applying the method are also provided.

Method of improving efficiency of updating data as to rules stored in block chain, electronic device, and computer readable storage medium applying the method

The invention provides a method of test pattern generation for an integrated circuit (IC) design simulation system, comprising merging at least 2 test vectors into a merged vector, wherein each test defines a set of test behaviors, and compiling and linking the merged vector using the IC design simulation system to generate a merged test pattern able to perform each set of test behaviors independently.

Method of test pattern generation in IC design simulation system

The design flow method of the present invention accurately performs timing analysis during the circuit design stage, so that the DFT synthesis procedure can effectively control the timing information, preventing timing violation from happening during the IC design flow process. Furthermore, the information of the CTS procedure and the static-timing analysis procedure is combined to perform accurate timing estimation.

Design flow method for integrated circuits

The invention provides a method of placement and routing for an array device in an integrated circuit (IC). In the method, a schematic script file used to describe placement for the array device is created according to a netlist and an array structure specification. The schematic script file is loaded into an auto P&R tool. The auto P&R tool is executed for completely routing the array device. After routing, an RC extraction can be directly implemented. Thus, product development time is greatly shortened.

Method of placement and routing for an array device

A method of automatic placement for an arrayed-element device, which automatically generates a schematic script for the arrayed-element device based on topological specifications, a netlist, and other parameters of the arrayed-element device, is disclosed. The generated schematic script can be loaded into an automatic place and route (P&R) tool to perform an automatic P&R which is available for RC extraction if completed so that time frame required by manual P&R and file conversion can be significantly reduced.

Growing community of inventors

Taipei, Taiwan

Chun-Chih Yang