Vanguard International Semiconductor Corporation

Qbic Technology Co., Ltd.

Chiun Mai Communication Systems, Inc.

Chun-Chih Chen

Shao-Chang Huang

Chih-Hsuan Lin

Kai-Chieh Hsu

Li-Fan Chen

Ching-Ho Li

Yeh-Ning Jou

Ting-You Lin

Yi-Hsin Chen

Ren-Yin Wu Ji

Gong-Kai Lin

Hwa-Chyi Chiou

Yu-Kai Wang

Chien-Wei Wang

Wen-Hsin Lin

Chien-Hsien Song

Hsiao-Ying Yang

Jung-Tsun Chuang

Hung-Wei Chen

Kuan-Chang Lin

Ching-Wen Wang

Mong-Hau Tsai

Fu-Chun Tseng

Chien-Chi Hsu

A level shifter includes a level shifting circuit and a voltage tracking circuit. The level shifting circuit receives an input signal through an input terminal and converts the input signal from a first power domain to a second power domain to generate an output signal at an output terminal. The voltage tracking circuit is coupled to first and second voltage terminals, and tracks one with a lower level among voltages of the first and second voltage terminals to generate a control voltage. The level shifting circuit includes first and second N-type transistors. The first N-type transistor has a gate coupled to the input terminal, a drain coupled to a first node, and a source coupled to a ground. The second N-type transistor has a gate receiving the control voltage, a drain coupled to the output terminal at a second node, and a source coupled to the input terminal.

Level shifter

An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes first, second, and third transistors and a discharge circuit. The first transistor has a first gate, a first drain coupled to the bonding pad, and a first source coupled to a first node. The second transistor has a second gate coupled to a power terminal, a second drain coupled to the first gate, and a second source coupled to a ground. The third transistor has a third gate coupled to the power terminal, a third drain coupled to the first node, and a third source coupled to the ground. The discharge circuit is controlled by a driving voltage at the first node. In response to an electrostatic discharge event occurring on the bonding pad, the discharge circuit provides a discharge path between the bonding pad and the ground according to the driving voltage.

Electrostatic discharge protection circuit and electronic circuit

A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.

Voltage tracking circuits with low power consumption and electronic circuits using the same

A semiconductor structure, including a substrate, a first well, a second well, a first doped region, a second doped region, a first gate structure, a first insulating layer, and a first field plate structure. The first and second wells are disposed in the substrate. The first doped region is disposed in the first well. The second doped region is disposed in the second well. The first gate structure is disposed between the first and second doped regions. The first insulating layer covers a portion of the first well and a portion of the first gate structure. The first field plate structure is disposed on the first insulating layer, and it partially overlaps the first gate structure. Wherein the first field plate structure is segmented into a first partial field plate and a second partial field plate separated from each other along a first direction.

Semiconductor structure

A voltage tracking circuit is provided and includes first and second P-type transistors and a voltage reducing circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The voltage reducing circuit is coupled between the first voltage terminal and the gate of the first P-type transistor. The voltage reducing circuit reduces a first voltage at the first voltage terminal by a modulation voltage to generate a control voltage and provides the control voltage to the gate of the first P-type transistor. The gate of the second P-type transistor is coupled to the first voltage terminal, and the drain thereof is coupled to a second voltage terminal. The source of the first P-type transistor and the source of the second P-type transistor are coupled to the output terminal of the voltage tracking circuit. The output voltage is generated at the output terminal.

Voltage tracking circuits and electronic circuits

An operating circuit is provided. A first N-type transistor determines whether to create an open circuit between a core circuit and a ground terminal according to the voltage level of a specific node. An electrostatic discharge (ESD) protection circuit is coupled between an input/output pad and the core circuit to prevent an ESD current from passing through the core circuit. The ESD protection circuit includes a detection circuit and a releasing element. The detection circuit determines whether there is an ESD event at the input/output pad and generates a first detection signal according to the detection of the ESD event at the input/output pad. The releasing element provides a release path according to the first detection signal to release the ESD current. A control circuit controls the voltage level of the specific node according to the first detection signal.

Operating circuit having ESD protection function

A semiconductor device includes a semiconductor substrate, a Schottky layer, a plurality of first doped regions, a plurality of second doped regions, a first conductive layer and a second conductive layer. The semiconductor substrate includes a first conductive type, and the Schottky layer is disposed on the semiconductor substrate. The first doped regions and the second doped regions include a second conductive type, and which are disposed within the semiconductor substrate. The first doped regions are in parallel and extended along a first direction, and the second doped regions are in parallel and extended along a second direction to cross the first doped regions, thereby to define a plurality of grid areas. The first conductive layer is disposed on the Schottky layer, and the second conductive layer is disposed under the semiconductor substrate.

Semiconductor device

A driving circuit including a detection circuit, a first control circuit, a second control circuit, and a driving transistor is provided. The detection circuit is coupled between a first power terminal and a second power terminal and generates a detection signal according to the voltages of the first and second power terminals. The first control circuit generates a first control signal according to the detection signal. The second control circuit generates a second control signal according to the detection signal. The driving transistor is coupled between an input-output pad and the second power terminal. When the detection signal is at a first level, the driving transistor is turned on according to the first control signal. When the detection signal is at a second level, the driving transistor is configured to operate according to the second control signal. The first level is different from the second level.

Driving circuit having electrostatic discharge protection

An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.

Electrostatic discharge protection circuit

Presence detector

Integrated display terminal device

Portion of an integrated display terminal device

A protective cover for portable electronic device includes a main body, a display module and a connecting module. The main body includes a first cover and a second cover that is foldable relative to the first cover. The second cover is configured to detachably attach the portable electronic device. The display module is attached to the first cover. The connecting module is attached to the second cover and electronically coupled to the display module. The connecting module is configured to receive display information from the portable electronic device and output the display information to the display module.

Protective cover and portable electronic device assembly employing the same

Growing community of inventors

Taipei, Taiwan

Chun-Chih Chen