Silicon Integrated Systems Corporation

Chun-Chieh Wu

Jen-Pin Su

Wen-Hsiang Lin

Tsan-Hui Chen

Chao-Yu Chen

Chang-Fu Lin

A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state. Subsequently, the configuration value fetched from the non-volatile memory is asserted to the at least one configurable device to configure the configurable device, and then the processor reset signal is deasserted, and the at least one configurable device is thereby completely configured.

Method and apparatus for reducing strapping devices

The present invention discloses an apparatus and system for multi-stage event synchronization, whose main object is to eliminate the drawbacks of an expensive synchronization circuit used to balance the data transmissions between an origination agent and a destination agent operating at different frequencies or clock phases as in prior art. The apparatus of the present invention organizes the slower one with multi-stage chains, each of which comprises a simple synchronization circuit and an XOR gate, for receiving the number of events transmitted from the faster one. Therefore, the slower one will not miss the data from the faster one.

Apparatus and system for multi-stage event synchronization

In a memory controller system, a method for granting a system memory by a memory request arbitrator to a request among a plurality of pending memory access requests is provided. The plurality of the memory access requests includes Rfrsh_Hreq, Crt_Hreq, Group AB, Crt_Lreq and Rfrsh_Lreq and are respectively asserted by a host control circuitry and/or a graphical control circuitry which are implemented and integrated on a single monolithic semiconductor chip. The host control circuitry and the graphical control circuitry shares the system memory and the memory request arbitrator includes a refresh queue and the graphics control circuitry includes a CRT FIFO. The method prioritizes the plurality of the memory access requests in order of Rfrsh_Hreq>Crt_Hreq>Group AB>Crt_Lreq>Rfrsh_Lreq. The Rfsh_Hreq is memory refresh request signal of first type whenever the refresh queue being full, the Crt_Hreq is memory access signal of a first type for fueling the CRT FIFO with display data, the Group AB are memory access request signals of a second type output either from the graphical control circuitry or the host control circuitry, the Crt_Lreq is memory access signal of a third type for fueling the CRT FIFO with display data, the Rfrsh_Lreq is memory refresh request signal of second type whenever the refresh queue being non-empty.

Growing community of inventors

Taichung, Taiwan

Chun-Chieh Wu