Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Chun-Chieh Lin

Yee-Chia Yeo

Hung-Wen Su

Chenming Hu

Wen-Chin Lee

Ya-Lien Lee

Liang-Guang Chen

Rueijer Lin

Fu-Ming Huang

Ting-Kui Chang

Fu-Liang Yang

Chien-Chao Huang

Kei-Wei Chen

Li-Chieh Wu

Ting-Hsun Chang

Chao-Hsiung Wang

Ming-Hsing Tsai

Cheng-Hui Weng

Syun-Ming Jang Jang

Chih-Hsin Ko

Chia-Pang Kuo

Chi-Hsiang Shen

Ji Cui

Hung Yen

Chih Hung Chen

Chi-Jen Liu

Minghsing Tsai

Chang-Sheng Lin

Kuo-Feng Huang

Kai-Shiang Kuo

Tang-Kuei Chang

Chien Chung Huang

Chih-Yi Chang

Yao-Min Liu

Huei-Wen Hsieh

Chen Ming Hu

Wei-Wei Liang

Cheng-Lun Tsai

Chien-Hao Chung

Chih-Hao Wang

Chia-Shiung Tsai

Shau-Lin Shue

Shih-Chang Chen

Mong-Song Liang

Kuo-Nan Yang

Pang-Yen Tsai

Lan-Lin Chao

Liang-Gi Yao

Chien-An Chen

Chen-Yuan Kao

Chia-Hui Lin

Huang-Yi Huang

Hsin-Ying Ho

Chih-Cheng Chen

Kao-Feng Liao

Shang-Chih Chen

Chung-Hsien Chen

Chuan-Yi Lin

Peng-Chung Jangjian

Wen-Jiun Liu

Chun-Sheng Chen

Chun-Wen Hsiao

Ji James Cui

Sheng-Chao Chuang

Win Hung

Wei-Hua Hsu

Yu-En Percy Chang

Chung Li Chang

Chi-Feng Cheng

Kishimoto Ko

Fu-Liaog Yang

Chanming Hu

Jen-Wei Liu

Michael Yen

Wei-Hsiang Chan

Ming-Hsiao Hsieh

Hun-Jan Tao

Baw-Ching Perng

Yen-Chun Lin

Yi-Chun Huang

Chung-Hu Ge

Shu-Cheng Chin

Hua-Gang Chang

Lawrence Chiang Sheu

Wong-Cheng Shih

Wen-Hsuan Chen

Ming-Yuan Gao

Ming Hsing Tsai

Ya-Ling Chen

Fu-ming Huang

Huan-yu Shih

Di-Bao Wang

Bow-Wen Chan

Howard Chih Hao Wang

Ye-Chia Yeng

Tsung Hsien Chang

Ming-Chou Chiang

A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.

Via for semiconductor device and method

The invention provides a silicide capacitive micro electromechanical structure and fabrication method thereof, comprising a substrate, a passivation layer, a silicon layer, a first metal layer, and a dielectric layer. The passivation layer is formed on the substrate; the silicon layer and the first metal layer are formed on the passivation layer. The first metal layer includes a contact part and a conductive part. The contact parts contact at least a part of the silicon layer, and the conductive portion extends away from the silicon layer to electrically connect an external circuit. The dielectric layer is formed on the passivation layer, and at least the silicon layer and the first metal layer are covered by the dielectric layer. After an annealing process is performed, the conductive portion remains in contact with the silicon layer after the silicidation reaction to maintain an electrical connection with the external circuit.

Silicide capacitive micro electromechanical structure and fabrication method thereof

A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.

Chemical mechanical planarization tool

A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.

Post-CMP cleaning and apparatus

In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.

Ruthenium-based liner for a copper interconnect

An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.

Thermally stable copper-alloy adhesion layer for metal interconnect structures and methods for forming the same

A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.

Methods for chemical mechanical polishing and forming interconnect structure

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.

Interconnect structure having a carbon-containing barrier layer

A chemical mechanical planarization apparatus includes a multi-zone platen comprising a plurality of individually controlled concentric toroids. The rotation direction, rotation speed, applied force, relative height, and temperature of each concentric toroid is individually controlled. Concentric polishing pads are affixed to an upper surface of each of the individually controlled concentric toroids. The chemical mechanical planarization apparatus includes a single central slurry source or includes individual slurry sources for each individually controlled concentric toroid.

Chemical mechanical polishing apparatus including a multi-zone platen

A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.

Diffusion barrier for semiconductor device and method

A method for CMP includes following operations. A metal layer is received. A CMP slurry composition is provided in a CMP apparatus. The CMP slurry composition includes at least a first oxidizer and a second oxidizer different from each other. The first oxidizer is oxidized to form a peroxidant by the second oxidizer. A portion of the metal layer is oxidized to form a first metal oxide by the peroxidant. The first metal oxide is re-oxidized to form a second metal oxide by the second oxidizer.

Chemical mechanical polishing slurry composition, method for chemical mechanical polishing and method for forming connecting structure

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Hsin-Chu, Taiwan

Chun-Chieh Lin