Silicon Motion, Inc.

Chun-Chieh Kuo

Tsung-Chieh Yang

Ching-Hui Lin

Yang-Chih Shen

Hong-Jung Hsu

Hsueh-Chun Fu

Shou-Wei Lee

A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Flash memory controller

The invention introduces a non-transitory computer program product for scheduling execution of host commands when executed by a processing unit of a flash controller. Space of a random access memory of the flash controller is allocated for a first queue and a second queue, and the first queue stores the host commands issued by a host side in an order of time when the host commands arrive to the flash controller. The non-transitory computer program product includes program code to: migrate one or more host write commands from the top of the first queue to the second queue in an order of time when the host write commands arrive to the flash controller until the top of the first queue stores a host read command; fetch the host read command from the top of the first queue; execute the host read command to read user data from a flash module; and reply to the host side with the user data.

Computer program product and method and apparatus for scheduling execution of host commands

A garbage collection method for a data storage device includes steps of: entering a background mode from a foreground mode; selecting a plurality of source data blocks from a plurality of in-use data blocks; dividing a mapping table into a plurality of sub-mapping tables and selecting one of the sub-mapping tables as a target sub-mapping table, wherein the target sub-mapping table is used to manage one of the source data blocks; selecting a destination data block from a plurality of spare data blocks; and sequentially updating a correspondence relationship of data stored in the target sub-mapping table from the source data blocks to the destination data block, wherein the updating comprises copying the data stored in the source data blocks to the destination data block.

Garbage collection method for data storage device

A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode.

A flash memory controller includes a recording medium and a processing circuit. When the amount of stored data in a flash memory module is less than a first threshold, the processing circuit controls a read and write circuit of the flash memory module to program a target data block using program threshold voltages within a first voltage range so as to write data into the target data block. When the amount of stored data in the flash memory module is greater than a second threshold, the processing circuit controls the read and write circuit to program the target data block using program threshold voltages within a second voltage range so as to write data into the target data block, wherein the second threshold is greater than the first threshold and the first voltage range is less than the second voltage range.

The invention provides a flash memory apparatus. In one embodiment, the flash memory apparatus comprises a flash memory and a flash memory controller. The flash memory comprises a write circuit and a memory cell array comprising a plurality of memory cells, wherein the write circuit is coupled to the memory cell array to write data in the memory cells. The flash memory controller is coupled to the write circuit, obtains a total capacity and a used data amount of the flash memory, and directs the write circuit to perform data writing in a one-bit mode when a ratio of the user data amount to the total capacity is less than a first predetermined value.

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Taipei, Taiwan

Chun-Chieh Kuo