United Microelectronics Corp.

Chun-Chieh Huang

Feng-Yu Hsu

Chih-Chien Liu

Su-Jen Sung

Jei-Ming Chen

Shing-Ren Sheu

Mei-Ling Chen

Wei-Chih Chen

Shu-Jen Sung

Dong-Chie Liou

Jiann-Jen Chiou

A method for manufacturing a multi cap layer includes providing a substrate, forming a multi cap layer comprising a first cap layer and a second cap layer formed thereon on the substrate, forming a patterned metal hard mask layer on the multi cap layer, and performing an etching process to etch the multi cap layer through the patterned hard mask layer and to form an opening in the second cap layer.

Method for manufacturing a dual damascene opening comprising a trench opening and a via opening

A device under test (DUT) array provides defect information rapidly and systematically. The DUT array includes a plurality of test units arranged in a matrix, a plurality of bit lines and a plurality of word lines. Each test unit has a first terminal and a second terminal. Each second terminal of the test unit is electrically connected to a ground point. The first terminals of the test units are electrically connected to the bit lines. The word lines are coupled to the test units. Defects in the each test unit can be identified by providing voltages to the bit lines and the word lines. Accordingly, defects in various devices of an integrated circuit can be detected rapidly and systematically by applying signals to the DUT array.

Device under test array for identifying defects

An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer electrically connecting with the conductive part, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a UV cutting layer at least between the first and the second porous low-k layers, wherein the UV cutting layer is a UV reflection layer or a UV reflection-absorption layer.

Interconnect structure and fabricating method thereof

A burn-in method for synchronous memory that utilizes synchronous signals for the burn-in operation. Using synchronous clock pulse signals for burning in the synchronous memory is able to exercise the burst output mode and the pipeline function, and hence the optimum burn-in results can be obtained. Furthermore, synchronous burn-in not only can increase the processing speed up to twice the conventional asynchronous burn-in method, but can simulate of the actual working environment of the synchronous memory as well. Moreover, an asynchronous burn-in method can be selected whenever required without any penalty.

Sychronous memory burn-in method

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Tainan Hsien, Taiwan

Chun-Chieh Huang