Realtek Semiconductor Inc.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Chun-Chieh Chan

Chia-Hao Chang

Shih-Ho Lin

Yu-Chen Wei

Jen-Chieh Lai

Tai-Jung Wu

Chun-Jui Chu

Chien-Hsun Lu

Ming-An Wu

Jheng-Si Su

Wei-lun Huang

Hung-Shao Chen

Heng-Yi Chen

Hsing-Yu Lin

Yi-Cheng Lin

Yen-Hung Lin

Che-Wei Yeh

Wen-Hsia Kung

Hsi-Pin Ma

Hung-Chih Chiu

Chia-Lung Hung

Ying-Hsin Lin

Yung-Ming Lin

Yi-Han Peng

Yi-cheng Lin

Yi-Lwun Ho

Tzung-Dau Wang

Hung-Chun Lu

Yu-Le Shen

Zhan-Yao Gu

Chia-fen Lin

Ying-Ying Song

Tzu-hsin Fan

An analog to digital converter includes voltage divider circuits, front-end circuits, at least one converter circuit, and a controller circuit. The voltage divider circuits are configured to divide an input signal to generate first signals, in which the first signals have different levels. The front-end circuits are configured to respectively sample the first signals to generate second signals. The at least one converter circuit is configured to generate at least one digital output according to the second signals and a reference voltage. The controller circuit is configured to determine a level of the input signal according to the at least one digital output and select one of the at least one digital output according to the level of the input signal.

Analog to digital converter having mechanism of detecting input voltage range and signal conversion method thereof

The present disclosure discloses a signal relay apparatus having frequency locking mechanism that includes a receiving circuit, a frequency generation circuit, a frequency tracking circuit and a transmission circuit. The receiving circuit receives a receiving signal to retrieve data included therein according a corresponding receiving frequency signal. The frequency generation circuit receives a source clock signal and generates a target frequency signal according to a conversion parameter. The frequency tracking circuit calculates a frequency difference between the receiving frequency signal and the target frequency signal to adjust the conversion parameter accordingly. The transmission circuit generates a transmission signal that includes the data according to the target frequency signal.

Signal relay apparatus and method having frequency locking mechanism

A multimedia system and a protocol converter are provided. The multimedia system includes a sink device, e.g., a television, various audiovisual devices connected to the sink device, and the protocol converter. The protocol converter is connected to the sink device, and processes the audio and video signals inputted from a specific audiovisual source and outputted to the sink device to be played. The audio signals can be processed and played by an audio playback device directly connected with the protocol converter. Furthermore, the protocol converter can process the audio signals being returned from the sink device of the multimedia system via an audio return channel or an enhanced audio return channel. Finally, the received audio signals are converted and outputted to one of various audio output interfaces supported by the protocol converter.

Integrated circuitry of speaker

A chemical mechanical polishing (CMP) apparatus is provided, including a polishing pad and a polishing head. The polishing pad has a polishing surface. The polishing head is configured to hold a wafer in contact with the polishing surface during the polishing process. The polishing head includes a retaining ring, at least one fluid channel, and a vacuum pump. The retaining ring is arranged along the periphery of the polishing head and configured to retain the wafer. The at least one fluid channel is provided inside the polishing head, wherein the retaining ring includes a bottom surface facing the polishing surface and a plurality of holes in fluid communication with the bottom surface and the at least one fluid channel. The vacuum pump is fluidly coupled to the at least one fluid channel.

Chemical mechanical polishing apparatus and method

A storage device sharing system and a storage device sharing method are provided. The storage device sharing system includes a storage device, a first chip and a second chip. The first chip and the second chip are configured to enter a toggle mode and an arbitration mode. In the toggle mode, the first chip that acts as the master controls the arbitration potential to a first control potential and a second control potential, and communicates with the storage device in response to the arbitration potential being the first control potential, and the second chip that acts as a slave communicates with the storage device in response to the arbitration potential being the second control potential.

Storage device sharing system and storage device sharing method

A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The second layer is in direct contact with the stop layer. The method includes partially removing the second layer. The method includes performing an etching process to partially remove the stop layer and an upper portion of the first layer, wherein protrusion structures are formed over a lower portion of the first layer after the etching process, and the protrusion structures include the stop layer and the upper portion of the first layer remaining after the etching process. The method includes removing the protrusion structures.

Method for forming semiconductor device structure

The present disclosure discloses a video interface conversion device that includes a first and a second interface transmission circuit, a color conversion circuit and an image compression circuit. The first and the second interface transmission circuit are respectively electrically coupled to an image source and a display terminal. The second interface transmission circuit negotiates a maximum output bandwidth with the display terminal such that the first interface transmission circuit compares an input data bandwidth of a data signal received from the image source and the maximum output bandwidth. When the maximum output bandwidth is smaller than the input data bandwidth, an image compression and/or a color coding conversion is performed on the data signal, and the data signal having the processed input data bandwidth being smaller than or equal to the maximum output bandwidth is further transmitted by the second interface transmission circuit to the display terminal.

Video interface conversion device and method

A method for switching audio-visual interfaces and a circuit system are provided. The circuit system is disposed in a sink device. A protocol layer circuit of each of audio-visual interfaces in the sink device includes a status and control data channel control module, which is used to respond to the signals sent by the video sources continuously when the sink device is connected with audio-visual sources via the audio-visual interfaces. The multiple video sources can accordingly send FRL (fixed rate link) signals to the sink device in response to responses made by the sink device. The protocol layer circuit includes an FRL audio-visual packet detection module that starts to detect a rate of an FRL and resolve audio-visual packets for obtaining audio-visual data for the audio-visual interface that the sink device switches to.

Method for switching audiovisual interfaces and circuit system

A chemical mechanical polishing method is provided, including polishing a batch of wafers in sequence on a polishing surface of a polishing pad; conditioning the polishing surface with a pad conditioner, wherein the pad conditioner is operable to apply downward force according to a predetermined downward force stored in a controller to condition the polishing surface; measuring the downward force applied by the pad conditioner with a measurement tool when the pad conditioner is at a home position and after conditioning the polishing surface; comparing the downward force measured by the measurement tool and the predetermined downward force with the controller to determine whether a difference between the downward force measured by the measurement tool and the predetermined downward force exceeds a range of acceptable values; and calibrating the downward force applied by the pad conditioner with the controller when the difference exceeds the range of acceptable values.

Chemical mechanical polishing method

A data conversion device includes a storage circuit and a frequency tuning circuit. The storage circuit is configured to store a pixel data in a high definition multimedia interface (HDMI) signal according to a first clock, and output an image data according to a second clock. The frequency tuning circuit is configured to adjust the second clock according to a control signal and the second clock in the HDMI signal, and transmit the adjusted second clock to the storage circuit.

Data conversion and high definition multimedia interface receiving device

The present invention discloses a signal relay apparatus having frequency calibration mechanism that includes a clock generation circuit, a frequency generation circuit, a clock measuring circuit, a frequency adjusting circuit and a transmission circuit. The clock generation circuit generates a source clock signal. The frequency generation circuit receives the source clock signal and generates a target frequency signal according to a conversion parameter. The clock measuring circuit measures a first frequency offset of a source frequency relative to a first predetermined frequency according to an external reference clock signal. The frequency adjusting circuit adjusts the conversion parameter according to the first frequency offset when the first frequency offset is not within a first predetermined range such that a second frequency offset of a target frequency relative to a second predetermined frequency is within a second predetermined range. The transmission circuit performs signal transmission according to the target frequency signal.

Signal relay apparatus and method having frequency calibration mechanism

An HDMI transmission device includes a packetizer circuit and a processor. A control method of controlling the HDMI transmission device includes performing a fixed rate link training, upon passing the fixed data rate link training, the processor transmitting an initial gap packet generation command to a controller of the packetizer circuit to output a selection signal to the packetizer circuit, so as to output an initial gap packet, when video data is not ready, continuously outputting the initial gap packet, when the video data is ready and a format change of the video data is detected or a signal abnormality unrelated to hot-plugging is detected, the processor transmitting a subsequent gap packet generation command to the controller to determine whether a block boundary is reached, and the controller switching the selection signal upon reaching the block boundary for the packetizer circuit to output the subsequent gap packet.

High definition multimedia interface transmission device and control method thereof

A video processing method and a video processor are provided. The video processing method can be utilized in a video processing system that includes a transmission terminal for generating an input video, the video processor, and a receiving terminal for receiving an output video. The method includes determining whether or not the input video is in at least one of an idle status, an unstable status and a terminated status; switching from outputting the output video to outputting a mute video when the input video is determined to be in at least one of the idle status, the unstable status and the terminated status; inserting a first general control packet for setting mute into one of a plurality of output frames of the mute video; and stopping outputting the mute video after the plurality of output frames of the mute video are outputted.

Video processing method and video processor

A dynamic voltage compensation circuit suitable for performing voltage compensation between an electronic device and a multimedia device, and includes a current detection unit, a calculation module and a voltage output unit. The current detection unit is configured to obtain the output current of the electronic device outputting the multimedia device from the bus power terminal. The calculation module is configured to receive the output current and an ideal reference voltage, execute a voltage compensation algorithm to calculate a predetermined output voltage based on the output current, the ideal reference voltage, and a compensation coefficient, and generate a control signal according to the predetermined output voltage. The voltage output unit is configured to receive a control signal, and is controlled by the control signal to generate a compensated output voltage and output it to a bus power terminal.

Dynamic voltage compensation circuit and method thereof

An image processing chip includes a first interface port, a second interface port, a first upstream facing port (UFP) physical layer module, a first configuration channel detection module, a second upstream facing port (UFP) physical layer module, a second configuration channel detection module, a display signal processing module, a USB signal processing module, an image signal output port and a USB signal output port. The first configuration channel detection module is coupled to the first interface port through a first configuration channel pair, and configured to, after being communicated through a USB specification, detect a first configuration channel signal of a first input signal group to determine a signal type of the first input signal group, and control the first UFP physical layer module to output the first input signal group with a first signal configuration according to the signal type of the first input signal group.

Growing community of inventors

Hsinchu, Taiwan

Chun-Chieh Chan