Winbond Electronics Corporation

Rexchip Electronics Corporation

Chun-Chiao Tseng

Kazuaki Takesako

Yoshinori Tanaka

Wei-Che Chang

Wei-Chih Liu

Chih-Wei Hsiung

Meng-Hsien Chen

Yukihiro Nagai

Yu-Ling Huang

Chung-Yung Ai

Chun-Hua Huang

Hirotake Fujita

Tomohiro Kadoya

Hsuan-Yu Fang

Hung-Ming Su

Yu-Shan Hsu

Chi-Hung Chan

Wen Kuei Hsu

Wen-Kuei Hsu

Provided is a semiconductor structure including a substrate, at least two tested structures, an isolation structure, and a short-circuit detection structure. At least two tested structures are disposed on the substrate. The at least two tested structures include a conductive material. The isolation structure is sandwiched between at least two tested structures. The detection structure includes a detecting layer, and the detecting layer is disposed on one of the at least two tested structures, so that a short circuit defect between the at least two tested structures may be identified in an electron beam detecting process, and the detecting layer includes a conductive material. A manufacturing method of the semiconductor structure and a method for detecting a short circuit of the semiconductor structure are also provided.

Semiconductor structure, manufacturing method thereof and method for detecting short thereof

A layout for measuring an overlapping state includes a layout region, a first dummy active area region, and dummy component regions. The first dummy active area region is located in the layout region. The dummy component regions are stacked in the layout region. At the moment when one of the dummy component regions is formed on the first dummy active area region, the one of the dummy component regions and the first dummy active area region have a first overlapping region, and the first overlapping region does not include other dummy component regions among the dummy component regions.

Layout for measuring overlapping state

A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.

Semiconductor device and method for making the same

A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.

Self-aligned wet etching process

Growing community of inventors

Taichung, Taiwan

Chun-Chiao Tseng