Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun-Chia Hsu

Li-Jui Chen

Shang-Chieh Chien

Po-Chung Cheng

Bao-Ru Young

Tung-Heng Hsieh

Chieh Hsieh

Bo-Tsun Liu

Tzung-Chi Fu

Yung Feng Chang

Yung-Feng Chang

Kuan-Hung Chen

Jam-Wem Lee

Chih-Hung Wang

Yu-Jung Chang

Tzung-Chi Lee

Chi Ming Yang

Yen-Shuo Su

Liu Bo-Tsun

A semiconductor structure includes a substrate having a first well of a first conductivity type and a second well of a second conductivity type. From a top view, the first well includes first and seconds edges extending along a first direction. The second edge has multiple turns, resulting in the first well having a protruding section and a recessed section. The semiconductor structure further includes a first source/drain feature over the protruding section and a second source/drain feature over a main body of the first well. The first source/drain feature is of the first conductivity type. The second source/drain feature is of the second conductivity type. The first and the second source/drain features are generally aligned along a second direction perpendicular to the first direction from the top view.

Semiconductor structures having wells with protruding sections for pickup cells

Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of semiconductor layers. The semiconductor layers are stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. A third conductive feature is formed over the first epitaxy region and within the oxide diffusion region. A fourth conductive feature is formed over the second epitaxy region and within the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.

ESD structure

An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.

Dummy poly layout for high density devices

Provided is a tap cell including a substrate, a first well, a second well, a first doped region, and the second doped region. The substrate has a first region and a second region. The first well has a first dopant type and includes a first portion disposed in the first region and a second portion extending into the second region. The second well has a second dopant type and includes a third portion disposed in the second region and a fourth portion extending into the first region. The first doped region having the first dopant type is disposed in the second portion of the first well and the third portion of the second well along the second region. The second doped region having the second dopant type is disposed in the first portion of the first well and the fourth portion of the second well along the first region.

Method of forming integrated circuit structure

Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first and second semiconductor layers are alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.

An apparatus for generating extreme ultraviolet (EUV) radiation includes a droplet generator configured to generate target droplets. An excitation laser is configured to heat the target droplets using excitation pulses to convert the target droplets to plasma. An energy detector is configured to measure a variation in EUV energy generated when the target droplets are converted to plasma. A feedback controller is configured to adjust parameters of the droplet generator and/or the excitation laser based on the variation in EUV energy.

Apparatus and method for generating extreme ultraviolet radiation

Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first semiconductor layers and the second semiconductor layers are alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions. Each of the first and second semiconductor layers has a first side contacting the first epitaxy region and a second side contacting the second epitaxy region, and the first side is opposite the second side.

ESD structure and semiconductor structure

Tap cell, integrated circuit structure and forming method thereof

A method for generating light is provided. The method further includes measuring a period of time during which one of targets from a fuel target generator passes through two detection positions. The method also includes exciting the targets with a laser generator so as to generate plasma that emits light. In addition, the operation of exciting the targets with the laser generator includes: irradiating a pre-pulse laser on the targets to expand the targets; detecting conditions of expanded targets; and adjusting at least one parameter of the laser generator according to the measured period of time and the conditions when the measured period of time is different from a predetermined value. The parameter of the laser generator which is adjusted according to the measured period of time includes a frequency for generating a laser for illuminating the targets.

Light source for lithography exposure process

A semiconductor structure includes a substrate having first and second wells of first and second conductivity types respectively. From a top view, the first and second wells extend lengthwise along a first direction, the first and second wells each includes a protruding section that protrudes along a second direction perpendicular to the first direction and a recessed section that recedes along the second direction. The protruding section of the first well fits into the recessed section of the second well, and vice versa. The semiconductor structure further includes first source/drain features over the protruding section of the first well; second source/drain features over the second well; third source/drain features over the protruding section of the second well; and fourth source/drain features over the first well. The first and second source/drain features are of the first conductivity type. The third and fourth source/drain features are of the second conductivity type.

A method for extreme ultraviolet (EUV) lithography includes loading an EUV mask to a lithography system; loading a wafer to the lithography system, wherein the wafer includes a resist layer sensitive to EUV radiation; producing EUV radiation by heating target plumes using a radiation source; and exposing the resist layer to the EUV radiation while monitoring a speed of the target plumes.

System and method for extreme ultraviolet source control

An apparatus for generating extreme ultraviolet (EUV) radiation comprises a droplet generator, an excitation laser source, an energy detector, and a feedback controller. The droplet generator is configured to generate target droplets. The excitation laser is configured to generate a pre-pulse and a main pulse to convert the target droplets to plasma by heating. The energy detector is configured to measure a variation in EUV energy generated when the target droplets are converted to plasma. The feedback controller is configured to adjust a time delay between a subsequent pre-pulse and main pulse generated by the excitation laser based on the variation in EUV energy generated by a given main pulse.

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Kaohsiung, Taiwan

Chun-Chia Hsu